公开(公告)号：US20150271699A1

公开(公告)日：2015-09-24

申请号：US14217615

申请日：2014-03-18

申请人： VIXS SYSTEMS INC.

发明人： Cheng-Chou Lan

IPC分类号： H04W28/02 ,  H04W72/08

CPC分类号： H04W28/0257 ,  H04L5/00 ,  H04L5/0007 ,  H04L5/0046 ,  H04L5/0048 ,  H04L5/006 ,  H04L5/0094 ,  H04W72/085

摘要： A device includes a signaling interface to receive OFDM signaling for an OFDM channel from multiple transmit nodes, an OFDM receiver to process the OFDM signaling, and a channel allocation module. The channel allocation module allocates subchannels of the channel among transmit nodes by: determining, for each transmit node, a corresponding SNR for each of the subchannels; assigning to each transmit node a corresponding subset of buckets of a set of buckets, the number of buckets in the subset based on a data rate requirement of the transmit node; distributing subchannels among the buckets based on the SNRs of the subchannels; and, for each transmit node, allocating to the transmit node the subchannels distributed to the subset of buckets assigned to the transmit node. The device further includes an OFDM transmitter to transmit configuration information to the transmit nodes, the configuration information representing the allocation of the subchannels.

摘要翻译： 一种设备包括用于接收来自多个发射节点的OFDM信道的OFDM信令的信令接口，用于处理OFDM信令的OFDM接收机以及信道分配模块。 信道分配模块通过以下方式分配发射节点之间的信道的子信道：对于每个发射节点，为每个子信道确定相应的SNR; 基于发送节点的数据速率要求，向每个发送节点分配一组桶的桶的相应子集，所述子集中的桶的数量; 基于子信道的信噪比分配子帧中的子信道; 并且对于每个发射节点，向发射节点分配分配给分配给发射节点的分组的子集的子信道。 该设备还包括OFDM发射机，用于向发射节点发送配置信息，该配置信息表示子信道的分配。

公开(公告)号：US20150271570A1

公开(公告)日：2015-09-24

申请号：US14590303

申请日：2015-01-06

申请人： VIXS Systems, Inc.

发明人： John Pomeroy ,  Xu Gang Zhao ,  Sally Jean Daub

IPC分类号： H04N21/81 ,  H04N21/845 ,  H04N21/262 ,  H04N21/41 ,  H04N21/84 ,  H04N21/2668 ,  H04N21/432 ,  H04N21/442 ,  H04N21/44

CPC分类号： H04N21/8133 ,  H04N21/26283 ,  H04N21/2668 ,  H04N21/4126 ,  H04N21/4325 ,  H04N21/44008 ,  H04N21/44222 ,  H04N21/812 ,  H04N21/84 ,  H04N21/8456

摘要： A user interest analysis generator analyzes input data corresponding to a viewing of the video program via the A/V player by at least one viewer, to determine a period of interest corresponding to the at least one viewer and to generate viewer interest data that indicates the period of viewer interest. An ad selection generator processes the viewer interest data and time coded metadata corresponding to the video program to automatically retrieve an advertisement from a remote ad server, corresponding to content of the video program during the period of interest, for display to the viewer by a display device.

摘要翻译： 用户感兴趣分析生成器通过至少一个观看者通过A / V播放器分析对应于视频节目的观看的输入数据，以确定与至少一个观看者相对应的兴趣周期，并产生指示 观众兴趣期。 广告选择生成器处理与视频节目相对应的观众感兴趣数据和时间编码元数据，以在感兴趣的时段期间自动从远程广告服务器检索与视频节目的内容相关的广告，以便通过显示器向观众显示 设备。

公开(公告)号：US20150271553A1

公开(公告)日：2015-09-24

申请号：US14590243

申请日：2015-01-06

申请人： ViXS Systems, Inc.

发明人： John Pomeroy ,  Xu Gang Zhao ,  Sally Jean Daub

IPC分类号： H04N21/466 ,  H04N21/472

CPC分类号： H04N21/4667 ,  H04N21/4126 ,  H04N21/42201 ,  H04N21/44204 ,  H04N21/472

摘要： A user interest analysis generator analyzes input data corresponding to a viewing of the video program via the A/V player by at least one viewer, to determine a period of interest corresponding to the at least one viewer and to generate viewer interest data that indicates the period of viewer interest. A metadata selection generator processes the viewer interest data and time coded metadata corresponding to the video program, and selects portions of the time coded metadata, corresponding to content of the video program during the period of interest, for display to the viewer by a display device.

摘要翻译： 用户感兴趣分析生成器通过至少一个观看者通过A / V播放器分析对应于视频节目的观看的输入数据，以确定与至少一个观看者相对应的兴趣周期，并产生指示 观众兴趣期。 元数据选择生成器处理与视频节目对应的观看者感兴趣数据和时间编码元数据，并且在感兴趣的时段期间选择对应于视频节目的内容的时间编码元数据的部分，以便通过显示设备向观看者显示 。

公开(公告)号：US20150271545A1

公开(公告)日：2015-09-24

申请号：US14217775

申请日：2014-03-18

申请人： ViXS Systems, Inc.

发明人： Paul D. Ducharme ,  Norman Vernon Douglas Stewart ,  Kuldip Sahdra ,  Krzysztof Socha ,  Chak Cheung Ho ,  Lewis Leung

IPC分类号： H04N21/426 ,  H04L29/06 ,  H04N21/44 ,  H04N21/2347 ,  H04N21/6377 ,  H04N21/434 ,  H04N21/4405

CPC分类号： H04N21/42623 ,  H04L63/0428 ,  H04N21/23103 ,  H04N21/2347 ,  H04N21/434 ,  H04N21/43853

摘要： A content access device includes an interface module that receives a transport stream and outputs a processed transport stream. An input buffer buffers the received transport stream. A polling processor processes the transport stream based on the at least one key to generate the processed transport stream, wherein the polling processor operates to descramble individual packets of the transport stream in a plurality of polling slots of a polling loop. An output buffer buffers the processed transport stream for output by the interface module.

摘要翻译： 内容访问设备包括接收模块，用于接收传输流并输出处理的传输流。 输入缓冲器缓冲接收的传输流。 轮询处理器基于至少一个密钥来处理传输流以生成经处理的传输流，其中轮询处理器操作以在轮询循环的多个轮询时隙中解扰传输流的各个分组。 输出缓冲器缓冲处理的传输流，以便由接口模块输出。

公开(公告)号：US09124233B2

公开(公告)日：2015-09-01

申请号：US12868617

申请日：2010-08-25

申请人： Hong Zeng

发明人： Hong Zeng

IPC分类号： H03G5/00 ,  H03G9/02 ,  H03G9/00

CPC分类号： H03G9/025 ,  H03G9/005

摘要： An audio equalizer includes an equalization processor that operates in conjunction with a transformed-based audio decoder that generates a decoded audio signal from an encoded audio signal. The equalization processor receives an equalization input signal, generates a plurality of response coefficients in response to the equalization input and applies the response coefficients to partially decoded data of the transformed-based audio decoder.

摘要翻译： 音频均衡器包括均衡处理器，其与基于变换的音频解码器相结合，该解码器从已编码的音频信号产生解码的音频信号。 均衡处理器接收均衡输入信号，响应于均衡输入产生多个响应系数，并将响应系数应用于基于变换的音频解码器的部分解码数据。

公开(公告)号：US09058297B2

公开(公告)日：2015-06-16

申请号：US14295479

申请日：2014-06-04

申请人： ViXS Systems, Inc.

发明人： Paul D. Ducharme ,  Norman Vernon Douglas Stewart

IPC分类号： G06F21/00 ,  G06F12/14 ,  G06F21/60 ,  G06F21/62 ,  G06F21/72 ,  G06F21/79

CPC分类号： G06F12/1408 ,  G06F21/00 ,  G06F21/10 ,  G06F21/602 ,  G06F21/6209 ,  G06F21/72 ,  G06F21/79 ,  G06F2221/2123 ,  G06F2221/2127 ,  G06F2221/2141 ,  H04N21/4181

摘要： A device includes a key store memory, a rule set memory, a plurality of cryptographic clients, and a key store arbitration module. The key store memory stores a plurality of cryptographic keys and the rule set memory stores a set of rules for accessing the cryptographic keys. A cryptographic client is operable to issue a request to access a cryptographic key(s) and, when access to the cryptographic key is granted, execute a cryptographic function regarding at least a portion of the cryptographic key to produce a cryptographic result. The key store arbitration module is operable to determine whether the request to access the cryptographic key is valid; when the request is valid, interpret the request to produce an interpreted request; access the rule set memory based on the interpreted request to retrieve a rule of the set of rules; and grant access to the cryptographic key in accordance with the rule.

摘要翻译： 设备包括密钥存储器存储器，规则集存储器，多个密码客户端和密钥存储仲裁模块。 密钥存储存储器存储多个加密密钥，并且规则集存储器存储用于访问加密密钥的一组规则。 加密客户端可操作以发出访问加密密钥的请求，并且当授权对加密密钥的访问时，执行关于密码密钥的至少一部分的加密功能以产生密码结果。 密钥存储仲裁模块可操作以确定访问加密密钥的请求是否有效; 当请求有效时，解释请求以产生解释的请求; 基于解释的请求访问规则集存储器以检索该组规则的规则; 并根据规则授予访问加密密钥的权限。

公开(公告)号：US20150163486A1

公开(公告)日：2015-06-11

申请号：US14100385

申请日：2013-12-09

申请人： Xinghai Li

发明人： Xinghai Li

IPC分类号： H04N19/93

CPC分类号： H04N19/115 ,  H04N19/14 ,  H04N19/177 ,  H04N19/194

摘要： A video processing device encodes an input video stream by dynamically varying an output bit rate for the resulting encoded video stream based on a length of the input video stream. A rate control module receives at least two parameters from an application requesting that the video stream be encoded: a target average bit rate (ABR) and a length of the video stream to be encoded. The rate control module varies the output bit rate according to the complexity of video information in the video stream and the remaining length of the video stream that has not been encoded. In addition, the rate control module constrains the output bit rate to ensure that the ABR is achieved for the entire encoded video stream.

摘要翻译： 视频处理设备通过基于输入视频流的长度动态地改变所得到的编码视频流的输出比特率来对输入视频流进行编码。 速率控制模块从请求视频流被编码的应用中接收至少两个参数：目标平均比特率（ABR）和待编码的视频流的长度。 速率控制模块根据视频流中的视频信息的复杂度和未被编码的视频流的剩余长度来改变输出比特率。 此外，速率控制模块限制输出比特率，以确保为整个编码视频流实现ABR。

公开(公告)号：US20150163484A1

公开(公告)日：2015-06-11

申请号：US14100373

申请日：2013-12-09

申请人： Xinghai Li

发明人： Xinghai Li

IPC分类号： H04N19/146

CPC分类号： H04N19/115 ,  H04N19/14 ,  H04N19/152 ,  H04N19/177

摘要： A video processing device encodes a set of multiple input video streams by varying an average bit rate for each input video stream within a corresponding set of bounded average bit rates identified based on a target average bit rate (TABR). To encode each input video stream, the rate control module identifies the amount of space remaining to store the encoded video streams and, based on this information and the TABR, calculates an upper bound average bit rate (UBABR) and lower bound average bit rate (LBABR) for the selected input video stream. The rate control module varies the output bit rate for the corresponding encoded video stream according to the complexity of video information in the video stream, but constrains the output bit rate to ensure that the average output bit rate is constrained within the UBABR and LBABR.

摘要翻译： 视频处理设备通过在基于目标平均比特率（TABR）识别的对应的有界平均比特率集合内改变每个输入视频流的平均比特率来对一组多个输入视频流进行编码。 为了对每个输入视频流进行编码，速率控制模块识别剩余的存储编码视频流的空间量，并且基于该信息和TABR，计算上限平均比特率（UBABR）和下限平均比特率 LBABR）用于所选择的输入视频流。 速率控制模块根据视频流中的视频信息的复杂度来改变对应的编码视频流的输出比特率，但限制输出比特率，以确保平均输出比特率被限制在UBABR和LBABR内。

公开(公告)号：US20150117535A1

公开(公告)日：2015-04-30

申请号：US14065605

申请日：2013-10-29

申请人： Xinghai Li ,  Xin Guo

发明人： Xinghai Li ,  Xin Guo

IPC分类号： H04N19/124 ,  H04N19/176 ,  H04N19/142

CPC分类号： H04N19/523 ,  H04N19/567 ,  H04N19/59

摘要： Reference pictures received via a video signal are downscaled to a specified resolution by a video encoder/decoder. For each current picture being processed by the video encoder/decoder, the current picture is maintained at its original received resolution, but is divided into blocks. Each block is further divided into sub-blocks, and each sub-block is compared, for a set of specified positions, to a corresponding block of the downscaled reference image to generate a set of candidate motion vectors. The candidate motion vectors are scored according to how closely their corresponding sub-block matches the corresponding block of the reference picture at the corresponding position, and a motion vector for each block of the current image is selected based on the scores. The selected motion vectors are used to process (e.g. encode) the video signal.

摘要翻译： 通过视频信号接收的参考图像被视频编码器/解码器缩减到指定的分辨率。 对于由视频编码器/解码器处理的每个当前图像，当前图像被保持在其原始接收分辨率，但是被划分成块。 每个块被进一步分成子块，并且对于一组指定位置将每个子块与缩小的参考图像的相应块进行比较，以生成一组候选运动矢量。 根据其对应的子块与对应位置处的参考图像的对应块的匹配程度对候选运动矢量进行刻痕，并且基于分数选择当前图像的每个块的运动矢量。 所选择的运动矢量用于处理（例如编码）视频信号。

公开(公告)号：US20150113594A1

公开(公告)日：2015-04-23

申请号：US14314691

申请日：2014-06-25

申请人： ViXS Systems, Inc.

发明人： Norman Vernon Douglas Stewart ,  Brian Lee

IPC分类号： H04L29/06

CPC分类号： H04L63/10 ,  G06F21/53 ,  G06F21/6281 ,  G06F21/74

摘要： A processing system includes a memory module that includes a plurality of memory blocks and a plurality of registers. A processor executes an operating system having a plurality of operating system processes, wherein each of the plurality of operating system processes is designated as a corresponding one of a plurality of virtual clients. A memory arbitration module receives a request to access a selected one of the plurality of memory blocks or registers from at least one of the plurality of virtual clients and determines whether or not to grant or deny the request, based on whether the selected memory block or register is designated for trusted or untrusted access and based on whether the virtual client is trusted or untrusted.

摘要翻译： 处理系统包括包括多个存储器块和多个寄存器的存储器模块。 处理器执行具有多个操作系统处理的操作系统，其中所述多个操作系统进程中的每一个被指定为多个虚拟客户机中的对应的一个。 存储器仲裁模块基于所选择的存储器块或所选择的存储器块是否接收从多个虚拟客户端中的至少一个访问多个存储器块或寄存器中的所选择的一个或多个虚拟客户端中的至少一个的请求，并且确定是否授予或拒绝该请求 寄存器被指定用于受信任或不受信任的访问，并且基于虚拟客户端是可信任还是不受信任的。