公开(公告)号：US12053263B2

公开(公告)日：2024-08-06

申请号：US17327317

申请日：2021-05-21

申请人： DermaSensor, Inc.

发明人： Steven Ryan Freiden ,  Warren Stewart Macchi ,  Cody Vance Simmons

IPC分类号： A61B5/00

CPC分类号： A61B5/0075 ,  A61B5/444 ,  A61B5/6843 ,  A61B2560/0233 ,  A61B2560/0238

摘要： Methods and devices are disclosed for calibrating intensity of a light source in a system of evaluating a skin lesion using Elastic-Scattering Spectroscopy (ESS). The ESS system may illuminate a sample of the skin lesion with a pulse from the light source adjusted to a high output setting, receive a signal comprising an elastic scattering spectrum from illuminating the skin lesion sample at the high output setting, determine whether the received signal has an intensity that is greater than a saturation threshold associated with at least one optical detection sensor, and if so, store the elastic scattering spectrum from illuminating the skin lesion sample at the high output setting. If not greater than the saturation threshold, the ESS system may illuminate the skin lesion sample with a pulse from the light source adjusted to a low output setting, receive a signal comprising an elastic scattering spectrum from illuminating the skin lesion sample at the low output setting, and store the elastic scattering spectrum from illuminating the skin lesion sample at the low output setting.

公开(公告)号：US12048759B2

公开(公告)日：2024-07-30

申请号：US17531407

申请日：2021-11-19

申请人： L'Oreal

发明人： Kimberly Christine Dreher ,  Gérard Provot ,  Dariusz Danielski ,  Fabien Pascal Boulineau ,  Caroline Rahmouna Françoise Goget ,  Anthony Potin ,  Allison Chin ,  Michael Degeorge ,  Mara Applebaum ,  Mary Abraam Soliman ,  Ashley Ann Figatner ,  Megan Pauker ,  Emmanuel Appiah-Amponsah

IPC分类号： A61K8/41 ,  A61K8/362 ,  A61K8/365 ,  A61Q5/00 ,  A61Q5/06 ,  A61Q5/08 ,  A61Q5/10 ,  A61Q5/12

CPC分类号： A61K8/41 ,  A61K8/362 ,  A61K8/365 ,  A61Q5/002 ,  A61Q5/08 ,  A61Q5/12 ,  A61K2800/43 ,  A61K2800/884 ,  A61Q5/065 ,  A61Q5/10

摘要： The disclosure relates to compositions for treating keratinous substrates, such as the hair, comprising at least one monoamine and at least one carboxylic acid, as well as systems and methods for treating keratinous substrates with the compositions.

公开(公告)号：USD1036302S1

公开(公告)日：2024-07-23

申请号：US29733015

申请日：2020-04-29

申请人： Manna Drones Limited

设计人： Miles Isted s'Jacob ,  Michael Isted ,  Buang Pattiata ,  Osasuyi Emumwen ,  Jamie Wedderburn ,  Tom Blake ,  Joe Gowans ,  Bobby Healy ,  Alan Hicks ,  Dan Moss ,  Arran Williams

摘要： FIG. 1 is a top/right side perspective view of the aircraft body.
FIG. 2 is a rear view of the aircraft body.
FIG. 3 is a front view of the aircraft body.
FIG. 4 is a left side view of the aircraft body.
FIG. 5 is a right side view of the aircraft body.
FIG. 6 is a top view of the aircraft body; and,
FIG. 7 is a bottom view of the aircraft body.
The broken lines shown in FIGS. 1-7 represent portions of the aircraft body that form no part of the claim.

公开(公告)号：US12040520B2

公开(公告)日：2024-07-16

申请号：US18348704

申请日：2023-07-07

申请人： Bloom Energy Corporation

发明人： Jessica Mahler ,  Chad Pearson ,  Rueben M. Kempton

IPC分类号： H01M8/249 ,  C25B1/042 ,  H01M8/04089 ,  H01M8/04276 ,  H01M8/0438 ,  H01M8/0656 ,  H01M8/12

CPC分类号： H01M8/249 ,  C25B1/042 ,  H01M8/04097 ,  H01M8/04276 ,  H01M8/0438 ,  H01M8/0656 ,  H01M2008/1293

摘要： A modular electrolyzer system including a power module and a generator module wherein the power module and the generator module are integrated with a hydrogen collection component and a steam delivery component, the hydrogen collection component and the steam delivery component being disposed on a structural base.

公开(公告)号：US12040289B2

公开(公告)日：2024-07-16

申请号：US17412530

申请日：2021-08-26

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Hong-Seng Shue ,  Ming-Da Cheng ,  Ching-Wen Hsiao ,  Yao-Chun Chuang ,  Yu-Tse Su ,  Chen-Shien Chen

IPC分类号： H01L23/58 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L23/585 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16227

摘要： An organic interposer includes interconnect-level dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the interconnect-level dielectric material layers, at least one dielectric capping layer located on a second side of the interconnect-level dielectric material layers, a bonding-level dielectric layer located on the at least one dielectric capping layer, metallic pad structures including pad via portions embedded in the at least one dielectric capping layer and pad plate portions embedded in the bonding-level dielectric layer, and an edge seal ring structure vertically extending from a first horizontal plane including bonding surfaces of the package-side bump structures to a second horizontal plane including distal planar surfaces of the metallic pad structures. The edge seal ring structure may include a vertical stack of metallic ring structures that are free of aluminum and laterally surround the package-side bump structures and the redistribution interconnect structures.

公开(公告)号：US12040267B2

公开(公告)日：2024-07-16

申请号：US18121189

申请日：2023-03-14

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Li-Ling Liao ,  Ming-Chih Yew ,  Chia-Kuei Hsu ,  Shu-Shen Yeh ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC分类号： H01L21/00 ,  H01L23/498 ,  H10K71/00

CPC分类号： H01L23/49838 ,  H01L23/49805 ,  H01L23/49822 ,  H10K71/621 ,  H01L23/49816

摘要： An organic interposer includes dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the dielectric material layers, and die-side bump structures located on a second side of the dielectric material layers. A gap region is present between a first area including first die-side bump structures and a second area including second die-side bump structures. Stress-relief line structures are located on, or within, the dielectric material layers within an area of the gap region in the plan view. Each stress-relief line structures may include straight line segments that laterally extend along a respective horizontal direction and is not electrically connected to the redistribution interconnect structures. The stress-relief line structures may include the same material as, or may include a different material from, a metallic material of the redistribution interconnect structures or bump structures that are located at a same level.

公开(公告)号：US12040019B2

公开(公告)日：2024-07-16

申请号：US18312635

申请日：2023-05-05

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Fu-Chen Chang ,  Chu-Jie Huang ,  Nai-Chao Su ,  Kuo-Chi Tu ,  Wen-Ting Chu

IPC分类号： G11C11/00 ,  G11C13/00 ,  H10N70/00 ,  H10N70/20

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0038 ,  H10N70/231 ,  H10N70/8833

摘要： Methods for programming memory cells of a resistive memory device include applying a voltage pulse sequence to a memory cell to set a logic state of the memory cell. An initial set sequence of voltage pulses may be applied to the memory cell, followed by a reform voltage pulse having an amplitude greater than the amplitudes of the initial set sequence, and within ±5% of the amplitude of a voltage pulse used in an initial forming process. Additional voltage pulses having amplitudes that are less than the amplitude of the reform voltage pulse may be subsequently applied. By applying a reform voltage pulse in the middle of, or at the end of, a memory set sequence including multiple voltage pulses, a resistive memory device may have a larger memory window and improved data retention relative to resistive memory devices programmed using conventional programming methods.

公开(公告)号：US12035520B2

公开(公告)日：2024-07-09

申请号：US17485949

申请日：2021-09-27

申请人： SANDISK TECHNOLOGIES LLC

发明人： Yanli Zhang ,  Peng Zhang

IPC分类号： H10B41/20 ,  H10B41/10 ,  H10B41/41 ,  H10B43/10 ,  H10B43/20 ,  H10B43/40

CPC分类号： H10B41/20 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H10B41/10 ,  H10B43/10

摘要： A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a semiconductor material layer, an inter-tier dielectric layer, and a second alternating stack of second insulating layers and second electrically conductive layers located over the inter-tier dielectric layer. A memory opening vertically extends through the second alternating stack, the inter-tier dielectric layer, and the first alternating stack. A memory opening fill structure is located in the memory opening, and includes a first vertical semiconductor channel, a second vertical semiconductor channel, and an inter-tier doped region located between the first and the second semiconductor channel, and providing a first p-n junction with the first vertical semiconductor channel and providing a second p-n junction with the second vertical semiconductor channel.

公开(公告)号：US12027728B2

公开(公告)日：2024-07-02

申请号：US18053834

申请日：2022-11-09

申请人： BLOOM ENERGY CORPORATION

发明人： Michael Gasda ,  Sachin Parhar ,  Cheng-Yu Lin ,  Victor Fung ,  Amit Nawathe ,  Brian Therault ,  Manoj Pillai

IPC分类号： H01M8/12 ,  C22C27/06 ,  C25B9/65 ,  H01M8/0208 ,  H01M8/0228 ,  H01M8/2425

CPC分类号： H01M8/0228 ,  C22C27/06 ,  C25B9/65 ,  H01M8/0208 ,  H01M8/12 ,  H01M8/2425 ,  H01M2008/1293

摘要： A method of making an interconnect for an electrochemical cell stack includes providing the interconnect, and creep flattening the interconnect prior to placing the interconnect into the electrochemical cell stack.

公开(公告)号：US12015050B2

公开(公告)日：2024-06-18

申请号：US17458706

申请日：2021-08-27

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Fu-Chiang Kuo

IPC分类号： H01G4/35 ,  H01L23/532 ,  H01L49/02

CPC分类号： H01L28/60 ,  H01G4/35 ,  H01L23/5329 ,  H01L28/91

摘要： A deep trench is formed in a substrate. A layer stack including at least three metallic electrode layers interlaced with at least two node dielectric layers is formed over the substrate. The layer stack continuously extends into the deep trench, and a cavity is present in an unfilled volume of the deep trench. A dielectric fill material layer including a dielectric fill material is formed in the cavity and over the substrate. The dielectric fill material layer encapsulates a void that is free of any solid phase and is formed within a volume of the cavity. The void may expand or shrink under stress during subsequently handling of a deep trench capacitor including the layer stack to absorb mechanical stress and to increase mechanical stability of the deep trench capacitor.