公开(公告)号：US20110145274A1

公开(公告)日：2011-06-16

申请号：US12639648

申请日：2009-12-16

Applicant: Gopal Avinash ,  Chetan Hd ,  Arun Kumar Chandrashekarappa ,  Arvind Kumar ,  Raja Shekhara

Inventor： Gopal Avinash ,  Chetan Hd ,  Arun Kumar Chandrashekarappa ,  Arvind Kumar ,  Raja Shekhara

IPC: G06F17/30 ,  G06F3/048

CPC classification number: G06F19/321

Abstract: Systems, methods and mediums with instructions for viewing medical data are provided. A system for viewing medical data can include a computer processor, a database and a user interface. The database can include numerous entries from numerous clinical modalities. Each entry can include image data and/or non-image data. Each entry can include annotated medical information from a previous study. The annotated medical information can include comments and markings. The database can be searchable to identify an entry based on input medical information relating to a current study. The user interface can be configured to simultaneously display annotated medical information from an identified entry and medical information from the current study. The system can further include a second user interface configured to display medical information, allow a user to annotate the medical information, and allow the user to save the annotated medical information as an entry in the database.

Abstract translation: 提供了具有查看医疗数据说明的系统，方法和介质。 用于查看医疗数据的系统可以包括计算机处理器，数据库和用户界面。 数据库可以包括许多临床模式的许多条目。 每个条目可以包括图像数据和/或非图像数据。 每个条目都可以包括以前研究的注释医学信息。 注释的医疗信息可以包括评论和标记。 可以搜索数据库以基于与当前研究相关的输入医疗信息来识别条目。 用户界面可以被配置为从当前研究中同时显示来自识别的条目的注释医学信息和医学信息。 该系统还可以包括被配置为显示医疗信息的第二用户界面，允许用户注释医疗信息，并允许用户将注释的医疗信息作为条目存储在数据库中。

公开(公告)号：US07956415B2

公开(公告)日：2011-06-07

申请号：US12133686

申请日：2008-06-05

Applicant: Anthony I. Chou ,  Andres Bryant ,  Arvind Kumar ,  Shreesh Narasimha

Inventor： Anthony I. Chou ,  Andres Bryant ,  Arvind Kumar ,  Shreesh Narasimha

IPC: H01L27/12

CPC classification number: H01L29/66772 ,  H01L29/78603 ,  H01L29/78612

Abstract: A top semiconductor layer is formed with two different thicknesses such that a step is formed underneath a body region of a semiconductor-on-insulator (SOI) field effect transistor at the interface between a top semiconductor layer and an underlying buried insulator layer. The interface and the accompanying interfacial defects in the body region provide recombination centers, which increase the recombination rate between the holes and electrons in the body region. Optionally, a spacer portion, comprising a material that functions as recombination centers, is formed on sidewalls of the step to provide an enhanced recombination rate between holes and electrons in the body region, which increases the bipolar breakdown voltage of a SOI field effect transistor.

Abstract translation: 顶部半导体层形成有两个不同的厚度，使得在顶部半导体层和下面的掩埋绝缘体层之间的界面处在绝缘体上半导体（SOI）场效应晶体管的体区之下形成台阶。 身体区域中的界面和伴随的界面缺陷提供了复合中心，这增加了身体区域中的空穴和电子之间的复合速率。 任选地，包括作为复合中心的材料的间隔物部分形成在台阶的侧壁上，以在体区中的空穴和电子之间提供增强的复合率，这增加了SOI场效应晶体管的双极击穿电压。

公开(公告)号：US07807712B2

公开(公告)日：2010-10-05

申请号：US11018923

申请日：2004-12-22

Applicant: Ram Pratap ,  Mavurapu Satyanarayana ,  Chandeshwar Nath ,  Ram Raghubir ,  Anju Puri ,  Ramesh Chander ,  Priti Tiwari ,  Brajendra Kumar Tripathi ,  Arvind Kumar Srivastava

Inventor： Ram Pratap ,  Mavurapu Satyanarayana ,  Chandeshwar Nath ,  Ram Raghubir ,  Anju Puri ,  Ramesh Chander ,  Priti Tiwari ,  Brajendra Kumar Tripathi ,  Arvind Kumar Srivastava

IPC: A61K31/36 ,  A61K31/427 ,  A61K31/085 ,  C07D317/06 ,  C07C49/105 ,  C07C49/11 ,  A61P3/10 ,  A61P9/10

CPC classification number: C07D295/092 ,  C07D277/34 ,  C07D317/54 ,  C07D417/12

Abstract: The present invention provides appropriately substituted chalcones, such as, for example, represented by the structural formula as shown herein below Wherein R1, R2 and R3 are selected from the group consisting of H, OH, O-alkyl, O-phenyl and O-substituted phenyl; B represents Ar—Z—O or RO; where Z is an alkane having up to 5 carbon atoms; R is substituted propanol amino, wherein substituted amino groups are selected from the group consisting of t-butyl, n-butyl, i-butyl, i-propyl, 4-phenyl piperazine-1-yl, 4-(2-methoxyphenyl)-piperazin-1-yl and 3,4-dimethoxy phenethyl; and Ar is thiazolidine-dione methylene phenoxy. The compounds prepared have been demonstrated to exhibit significant antidiabetic effect in various animal models indicating potential for further exploitation.

Abstract translation: 本发明提供适当取代的查尔酮，例如由如下文所示的结构式表示，其中R1，R2和R3选自H，OH，O-烷基，O-苯基和O- 取代的苯基; B表示Ar-Z-O或RO; 其中Z是具有至多5个碳原子的烷烃; R是取代的丙醇氨基，其中取代的氨基选自叔丁基，正丁基，异丁基，异丙基，4-苯基哌嗪-1-基，4-（2-甲氧基苯基） - 哌嗪-1-基和3,4-二甲氧基苯乙基; Ar是噻唑烷二酮亚甲基苯氧基。 已经证明所制备的化合物在各种动物模型中表现出显着的抗糖尿病作用，表明有可能进一步开发。

公开(公告)号：US20100194324A1

公开(公告)日：2010-08-05

申请号：US12365118

申请日：2009-02-03

Applicant: Bogdan Z. Kasztenny ,  Somakumar R. ,  Arvind Kumar Tiwari ,  Arijit Banerjee

Inventor： Bogdan Z. Kasztenny ,  Somakumar R. ,  Arvind Kumar Tiwari ,  Arijit Banerjee

IPC: H02H7/08

CPC classification number: G01R31/34 ,  G01R31/025 ,  G01R31/346

Abstract: A system and method are provided for correction of parameters used in determination of stator turn faults of an induction motor. An embodiment may include determining a residual impedance and/or a residual voltage of the motor, and correcting a normalized cross-coupled impedance based on the residual impedance and residual voltage. Additional embodiments may include measuring an operating temperature of the motor and determining a negative sequence impedance of the motor based on the temperature. Another embodiment may include measuring voltages and currents of the motor and determining phasors for the voltages and currents using compensation for variations from a nominal frequency of the motor.

Abstract translation: 提供了用于校正用于确定感应电动机的定子匝故障的参数的系统和方法。 实施例可以包括确定电动机的残余阻抗和/或剩余电压，以及基于残余阻抗和残余电压校正归一化的交叉耦合阻抗。 另外的实施例可以包括测量电动机的工作温度并基于温度确定电动机的负序阻抗。 另一个实施例可以包括测量电动机的电压和电流，并且使用对来自电动机的额定频率的变化的补偿来确定电压和电流的相量。

公开(公告)号：US20100164011A1

公开(公告)日：2010-07-01

申请号：US12720354

申请日：2010-03-09

Applicant: Martin M. Frank ,  Arvind Kumar ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Jeffrey Sleight

Inventor： Martin M. Frank ,  Arvind Kumar ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Jeffrey Sleight

IPC: H01L29/78

CPC classification number: H01L27/1104 ,  H01L27/11 ,  H01L27/1108

Abstract: Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.

Abstract translation: 提供了用于组合彼此具有不同阈值电压要求的晶体管的技术。 在一个方面，一种半导体器件包括具有第一和第二nFET区的衬底以及第一和第二pFET区; 在第一nFET区域上的衬底上的逻辑nFET; 在第一pFET区上的衬底上的逻辑pFET; 位于第二nFET区上的衬底上的SRAM nFET; 以及在第二pFET区上的衬底上的SRAM pFET，每个包括在高K层上具有金属层的栅极堆叠。 逻辑nFET栅极堆叠还包括将金属层与高K层分隔开的覆盖层，其中封盖层还被配置为相对于逻辑pFET中的一个或多个的阈值电压移动逻辑nFET的阈值电压 ，SRAM nFET和SRAM pFET。

公开(公告)号：US07725919B1

公开(公告)日：2010-05-25

申请号：US10154762

申请日：2002-05-23

Applicant: Balaji Thiagarajan ,  Sharad Garg ,  Arvind Kumar Peechara ,  Theodore Nguyen ,  Parichay Saxena

Inventor： Balaji Thiagarajan ,  Sharad Garg ,  Arvind Kumar Peechara ,  Theodore Nguyen ,  Parichay Saxena

IPC: H04N7/16

CPC classification number: H04N21/4147 ,  H04N5/76 ,  H04N5/765 ,  H04N5/775 ,  H04N5/781 ,  H04N5/782 ,  H04N21/4325 ,  H04N21/4331 ,  H04N21/4333 ,  H04N21/4335 ,  H04N21/4383 ,  H04N21/8456

Abstract: A short-term content buffer maintains segments of audio and/or video content and the content segments are identified with segment identifiers which enables management and playback of the content segments. In an embodiment, independent video content segments corresponding to a particular broadcast channel can be identified by associated content segment identifiers and the video content segments can be recorded together to generate a single recording of the content.

Abstract translation: 短期内容缓冲器维护音频和/或视频内容的段，并且内容片段使用能够管理和回放内容片段的片段标识符来标识。 在一个实施例中，对应于特定广播频道的独立视频内容片段可以由相关联的内容片段标识符识别，并且可以将视频内容片段记录在一起以生成内容的单个记录。

公开(公告)号：US20100077840A1

公开(公告)日：2010-04-01

申请号：US12459193

申请日：2009-06-26

Applicant: Arvind Kumar Srivastava ,  Vinayak P. Dravid

Inventor： Arvind Kumar Srivastava ,  Vinayak P. Dravid

IPC: G01N21/00 ,  G01N27/00 ,  G01J3/00

CPC classification number: G01N27/305 ,  G01N33/0034

Abstract: A light-assisted sensor and method of light-assisted sensing of gaseous species involves contacting a gaseous medium with a material selected to adsorb on its surface one or more gaseous species of interest and illuminating the surface of the material from a source to induce a change of an electrical property, such as conductivity, of the material in the presence of the one or more gaseous species. The change in the electrical property of the material is measured and can be used to identify and quantify the gaseous species of interest in the gaseous medium.

Abstract translation: 光辅助传感器和光辅助感测气态物质的方法包括使气体介质与选定成在其表面上吸附一种或多种感兴趣的气体物质的材料接触，并从源发射材料的表面以引起变化 具有在一种或多种气态物质存在下的材料的电性质，例如导电性。 测量材料的电性能的变化，并且可用于鉴定和量化气态介质中感兴趣的气态物质。

公开(公告)号：US07632127B2

公开(公告)日：2009-12-15

申请号：US12100480

申请日：2008-04-10

Applicant: Brian Samuel Beaman ,  Joseph Kuczynski ,  Theron Lee Lewis ,  Amanda Elisa Ennis Mikhail ,  Arvind Kumar Sinha

Inventor： Brian Samuel Beaman ,  Joseph Kuczynski ,  Theron Lee Lewis ,  Amanda Elisa Ennis Mikhail ,  Arvind Kumar Sinha

IPC: H01R13/62

CPC classification number: H01R12/7052 ,  H01R12/714 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49208 ,  Y10T29/53174 ,  Y10T29/53265

Abstract: The illustrative embodiments provide a socket, a method for manufacturing the socket, a device, and a method for compensating for differing coefficients of thermal expansion between a socket and a printed circuit board. The socket includes surface mounted contacts and an elongated housing. The elongated housing comprises at least two members that are coupled together and disposed to form an aperture in between the at least two members, wherein the surface mounted contacts extend from the aperture, and wherein at least one dimension of the at least two members is selected to compensate for a difference between the coefficients of thermal expansion between the socket and a printed circuit board.

Abstract translation: 说明性实施例提供插座，用于制造插座的方法，装置和用于补偿插座和印刷电路板之间的不同热膨胀系数的方法。 插座包括表面安装的触点和细长的外壳。 所述细长壳体包括至少两个联接在一起并设置成在所述至少两个构件之间形成孔的构件，其中所述表面安装的触点从所述孔延伸，并且其中所述至少两个构件的至少一个尺寸被选择 以补偿插座和印刷电路板之间的热膨胀系数之间的差异。

公开(公告)号：US20080258221A1

公开(公告)日：2008-10-23

申请号：US12144272

申请日：2008-06-23

Applicant: Robert H. Dennard ,  Wilfried E. Haensch ,  Arvind Kumar ,  Robert J. Miller

Inventor： Robert H. Dennard ,  Wilfried E. Haensch ,  Arvind Kumar ,  Robert J. Miller

IPC: H01L27/11

CPC classification number: H01L27/1108

Abstract: A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devices is doped to a specific level so as to improve the performance of the FET devices within the different device regions is provided. In particular, the back gate within the SRAM device region is more heavily doped than the back gate within the logic device region. In order to control short channel effects, the FET device within the logic device region includes a doped channel, while the FET device within the SRAM device region does not. A none uniform lateral doping profile with a low net doping beneath the source/drain regions and a high net doping underneath the channel would provide additional SCE control for the logic device.

Abstract translation: 一种半导体结构，其包括至少一个逻辑器件区域和至少一个静态随机存取存储器（SRAM）器件区域，其中每个器件区域包括双门控场效应晶体管（FET），其中每个FET器件的背栅极掺杂 提供了特定的水平，以提高不同器件区域内的FET器件的性能。 特别地，SRAM器件区域内的背栅极比逻辑器件区域内的后栅极重掺杂。 为了控制短沟道效应，逻辑器件区域内的FET器件包括掺杂沟道，而SRAM器件区域内的FET器件不是。 在源极/漏极区域之下具有低净掺杂的非均匀横向掺杂分布和在沟道下方的高净掺杂将为逻辑器件提供附加的SCE控制。

公开(公告)号：US07407871B2

公开(公告)日：2008-08-05

申请号：US11515534

申请日：2006-09-05

Applicant: Arvind Kumar ,  Keen Wah Chow ,  Devesh Kumar Datta ,  Subramanian Krishnan

Inventor： Arvind Kumar ,  Keen Wah Chow ,  Devesh Kumar Datta ,  Subramanian Krishnan

IPC: H01L21/322

CPC classification number: H01L21/26513 ,  H01L27/10873

Abstract: A process for fabricating an MOS device specifically a DRAM device, featuring passivation of defects in regions of a semiconductor substrate wherein defects left unpassivated can deleteriously influence data retention time, has been developed. A high density plasma dry etching procedure used to define the DRAM conductive gate electrode can create unwanted defects in a region near the surface of uncovered portions of the semiconductor substrate during the high density plasma procedure over etch cycle. Implantation of a group V element such as arsenic can be used to passivate the unwanted plasma etch defects, thus reducing the risk of defect related device leakage phenomena. However to insure the group V implanted species remain at or near the semiconductor surface for optimum defect passivation, the group V element implantation procedure is performed after all high temperature DRAM fabrication steps, such as selective oxidation for creation of oxide spacers on the sides of the conductive gate electrode, have been completed. A slow diffusing implanted arsenic ion is the optimum candidate for passivation while faster diffusing group V elements such as phosphorous are not as attractive for defect passivation.