公开(公告)号：US5946248A

公开(公告)日：1999-08-31

申请号：US32401

申请日：1998-02-27

Applicant: Pien Chien ,  Shih-Chin Lin ,  Charlie Han

Inventor： Pien Chien ,  Shih-Chin Lin ,  Charlie Han

IPC: G01R31/28 ,  G11C29/50 ,  G11C13/00

CPC classification number: G11C29/50 ,  G01R31/2856 ,  G11C11/401

Abstract: A method is provided for use on a wafer formed with a plurality of dice on each of which a memory device, such as a DRAM (dynamic random access memory) device to perform a burn-in operation on the memory device so as to test the reliability thereof. By this method, a plurality of pads are formed in the scribe lines that are used as reference marks in the cutting apart of the dice. These pads are used to transfer an externally generated burn-in enable signal and a DC bias voltage to each memory device. Since the pads for burn-in wiring are formed in the scribe lines, they will not take additional space on the dice where each memory device is formed. The burn-in operation is more convenient, quick, and cost-effective to implement.

Abstract translation: 提供一种在形成有多个骰子的晶片上使用的方法，每个骰子上具有诸如DRAM（动态随机存取存储器）设备的存储器件，以在存储器件上执行老化操作，以便测试 可靠性。 通过这种方法，在切割线中用作参考标记的划线中形成多个焊盘。 这些焊盘用于将外部产生的老化使能信号和直流偏置电压传送到每个存储器件。 由于用于老化线的焊盘形成在划线中，所以它们在形成每个存储器件的骰子上不会占用额外的空间。 老化操作更加方便，快捷，性价比高。

公开(公告)号：US06545350B2

公开(公告)日：2003-04-08

申请号：US09774789

申请日：2001-01-31

Applicant: Kai-Kuang Ho ,  Te-Sheng Yang ,  Charlie Han

Inventor： Kai-Kuang Ho ,  Te-Sheng Yang ,  Charlie Han

IPC: H01L2310

CPC classification number: H01L24/32 ,  H01L23/4334 ,  H01L23/4951 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012

Abstract: This invention relates to a method and a means for packaging integrated circuits, especially relates to a heat sink in the operating integrated circuit packages. The heat sink is bonded on the lead frame by a tap and take advantage of the length between the heat sink and the first mold packaged materials at the first axis to be about equal to the length between the chip and the second mold packaged materials at the first axis to prevent producing voids form unbalanceable thermal mold flow. The heat sink can also dissipating heat from the lead frame to others spaces in the integrated circuit packages. This method and means can prevent delaminating and cracking occurring in the chip and increasing the qualities in integrated circuits.