公开(公告)号：US5946248A

公开(公告)日：1999-08-31

申请号：US32401

申请日：1998-02-27

申请人： Pien Chien ,  Shih-Chin Lin ,  Charlie Han

发明人： Pien Chien ,  Shih-Chin Lin ,  Charlie Han

IPC分类号： G01R31/28 ,  G11C29/50 ,  G11C13/00

CPC分类号： G11C29/50 ,  G01R31/2856 ,  G11C11/401

摘要： A method is provided for use on a wafer formed with a plurality of dice on each of which a memory device, such as a DRAM (dynamic random access memory) device to perform a burn-in operation on the memory device so as to test the reliability thereof. By this method, a plurality of pads are formed in the scribe lines that are used as reference marks in the cutting apart of the dice. These pads are used to transfer an externally generated burn-in enable signal and a DC bias voltage to each memory device. Since the pads for burn-in wiring are formed in the scribe lines, they will not take additional space on the dice where each memory device is formed. The burn-in operation is more convenient, quick, and cost-effective to implement.

摘要翻译： 提供一种在形成有多个骰子的晶片上使用的方法，每个骰子上具有诸如DRAM（动态随机存取存储器）设备的存储器件，以在存储器件上执行老化操作，以便测试 可靠性。 通过这种方法，在切割线中用作参考标记的划线中形成多个焊盘。 这些焊盘用于将外部产生的老化使能信号和直流偏置电压传送到每个存储器件。 由于用于老化线的焊盘形成在划线中，所以它们在形成每个存储器件的骰子上不会占用额外的空间。 老化操作更加方便，快捷，性价比高。

公开(公告)号：US5995428A

公开(公告)日：1999-11-30

申请号：US32627

申请日：1998-02-27

申请人： Pien Chien ,  Shih-Chin Lin ,  Charlie Han

发明人： Pien Chien ,  Shih-Chin Lin ,  Charlie Han

IPC分类号： G01R31/28 ,  G11C29/50 ,  G11C29/00

CPC分类号： G11C29/50 ,  G01R31/2856 ,  G11C11/401

摘要： A circuit is provided for use on a wafer formed with a plurality of dice on each of which a memory device, such as a DRAM (dynamic random access memory) device to perform a burn-in operation on the memory device so as to test the reliability thereof. By this circuit, a plurality of pads are formed in the scribe lines that are used as reference marks in the cutting apart of the dice. These pads are used to transfer an externally generated burn-in enable signal and a DC bias voltage to each memory device. Since the pads for burn-in wiring are formed in the scribe lines, they will not take additional space on the dice where each memory device is formed. The burn-in operation is more convenient, quick, and cost-effective to implement.

摘要翻译： 提供了一种电路，用于在形成有多个骰子的晶片上使用，每个骰子具有诸如DRAM（动态随机存取存储器）设备的存储器件，以在存储器件上执行老化操作，以便测试 可靠性。 通过该电路，在切割线中用作参考标记的划线中形成多个焊盘。 这些焊盘用于将外部产生的老化使能信号和直流偏置电压传送到每个存储器件。 由于用于老化线的焊盘形成在划线中，所以它们在形成每个存储器件的骰子上不会占用额外的空间。 老化操作更加方便，快捷，性价比高。

公开(公告)号：US06711048B2

公开(公告)日：2004-03-23

申请号：US10134277

申请日：2002-04-25

申请人： Pien Chien

发明人： Pien Chien

IPC分类号： G11C1122

CPC分类号： G11C11/406 ,  G11C15/04 ,  G11C15/043

摘要： A 2-port memory device is provided. The 2-port memory device is necessary to be periodically refreshed to maintain the data stored in cells of the memory device. The memory device can be accessed by read/write operation and a refresh operation without any interference with each other. Such device can provide a very high speed accessing and the operating frequency of the memory device can be easily increased significantly.

摘要翻译： 提供2端口存储器件。 需要定期刷新2端口存储器件以维持存储在存储器件的单元中的数据。 可以通过读/写操作和刷新操作来访问存储器件，而不会彼此干涉。 这样的设备可以提供非常高的访问速度，并且可以容易地显着地增加存储器件的工作频率。

公开(公告)号：US20060190457A1

公开(公告)日：2006-08-24

申请号：US11033679

申请日：2005-01-13

申请人： Pien Chien

发明人： Pien Chien

IPC分类号： G06F17/30 ,  G06F7/00

CPC分类号： G06Q10/10

摘要： A method of increasing enterprise alliance or successful cooperation comprising collecting the basic information and the news information of several target units. According to the above basic information, the target units are classified into several classifications. An assessment is performed based on the above news information and the basic information, thereby generating several items and the item points. The corresponding classifications, the items and the items points of above target unit are stored. A plurality of electronic mails is transmitted to a portion of the target units depending on the above classifications, items and above items points. Therefore, some common consensuses are obtained or some titles are prepared from the specific contents of the electronic mails returned by the targeted partners.

摘要翻译： 增加企业联盟或成功合作的方法，包括收集几个目标单位的基本信息和新闻信息。 根据上述基本信息，目标单位分为几类。 基于上述新闻信息和基本信息进行评估，从而生成多个项目和项目点。 存储上述目标单位的相应分类，项目和项目点。 根据上述分类，项目和上述项目点，多个电子邮件被发送到目标单元的一部分。 因此，获得一些共同的共识，或者由目标合作伙伴返回的电子邮件的具体内容准备一些标题。

公开(公告)号：US6137730A

公开(公告)日：2000-10-24

申请号：US231151

申请日：1999-01-15

申请人： Pien Chien

发明人： Pien Chien

IPC分类号： G11C7/10 ,  G11C7/18 ,  G11C7/00

CPC分类号： G11C7/1048 ,  G11C7/18

摘要： A semiconductor integrated circuit device includes a plurality of memory cells subdivided into array blocks each including M cell rows and N cell columns. The array blocks are arranged in array block rows and array block columns. Each cell of each cell row of each array block is coupled to an associated one of M word lines. Each cell of each cell column is selectively coupled to develop a data signal transmitted between an associated bit line pair including a primary bit line and a complementary bit line. A row decoder is coupled to provide a corresponding row address signal to each of the M word lines for addressing the cell rows. Each array block column includes: a plurality of column multiplexers each including N multiplexer input ports connected to receive one of the data signals from one of the bit line pairs of an associated one of the array blocks, and a multiplexer output port providing the data signals from selected ones of the N multiplexer input ports; a plurality of intermediate sense amplifiers each having an amplifier input port connected to receive the data signals from a corresponding one of the multiplexer output ports, and an amplifier output port providing pre-amplified data signals; a plurality of column demultiplexers each including an input port connected to receive a pre-amplified data signal, and a plurality of demultiplexer output ports each connected to one of the bit line pairs of a corresponding one of the array blocks.

摘要翻译： 半导体集成电路器件包括被分成阵列块的多个存储单元，每个阵列块包括M个单元行和N个单元列。 阵列块被排列成数组块行和数组块列。 每个阵列块的每个单元行的每个单元被耦合到M个字线中的相关联的一个。 每个单元列的每个单元被选择性地耦合以形成在包括主位线和互补位线的相关位线对之间传输的数据信号。 行解码器被耦合以向M个字线中的每一个提供相应的行地址信号，用于寻址单元行。 每个阵列块列包括：多个列多路复用器，每个多路复用器包括N个多路复用器输入端口，该多路复用器输入端口被连接以接收来自相关联的一个阵列块的位线对之一的数据信号之一;以及多路复用器输出端口，提供数据信号 从N个多路复用器输入端口中选定的一个; 多个中间读出放大器，每个具有连接的放大器输入端口，以从多路复用器输出端口中相应的一个接收数据信号;以及放大器输出端口，提供预放大的数据信号; 每个包括连接以接收预放大数据信号的输入端口的多个列解复用器，以及多个解复用器输出端口，每个多路分用器输出端口连接到对应的一个阵列块的一个位线对。

公开(公告)号：US06760249B2

公开(公告)日：2004-07-06

申请号：US10176238

申请日：2002-06-19

申请人： Pien Chien

发明人： Pien Chien

IPC分类号： G11C1100

CPC分类号： G11C11/406 ,  G11C8/16 ,  G11C15/04 ,  G11C15/043

摘要： A NAND or NOR content-addressable memory (CAM) cell, which selectively use single port, tow ports, or three ports for operations depending on design requirements. Only n-channel transistors or p-channel transistors design these NAND or NOR CAM cells. In such designs, one-port bit line with one-port word line, or one-port bit line with two-port word lines, or two-port bit lines with two-port word lines are provided for meeting different operations and pruposes.

摘要翻译： NAND或NOR内容可寻址存储器（CAM）单元，其选择性地使用单端口，串口或三个端口用于根据设计要求进行操作。 只有n沟道晶体管或p沟道晶体管设计这些NAND或NOR CAM单元。 在这样的设计中，提供具有单端口字线的单端口位线或具有双端口字线的单端口位线或具有双端口字线的双端口位线，以满足不同的操作和pruposes。

公开(公告)号：US06556498B2

公开(公告)日：2003-04-29

申请号：US10047765

申请日：2002-01-14

申请人： Pien Chien

发明人： Pien Chien

IPC分类号： G11C700

CPC分类号： G11C15/04 ,  G11C11/406 ,  G11C15/043

摘要： An operation method for a static random access memory (SRAM) device. The SRAM device has a plurality of memory cells. Each of the memory cells is periodically refreshed to retain valid data. The operation method comprising receiving an access address and a refresh address for the SRAM device and detecting whether a transition pulse and a refresh pulse being generated. The access address is used for accessing data stored in the SRAM device and the refresh address is used for periodically refreshing the memory cell in the SRAM. The transition pulse is generated by an address transition detector when a read/write operation is issued. The refresh pulse is generated in response to a refresh clock being in an active state.

公开(公告)号：US06414898B1

公开(公告)日：2002-07-02

申请号：US09759907

申请日：2001-01-16

申请人： Pien Chien

发明人： Pien Chien

IPC分类号： G11C800

CPC分类号： G11C11/4087 ,  G11C7/1048 ,  G11C8/10 ,  G11C8/18 ,  G11C11/4096

摘要： A decode circuit provides timing and control signals to a DRAM to insure a minimum current surge during activation of bit-lines within the DRAM during a row address strobe (RAS) cycle. Providing the minimum current surge during the RAS cycle prevents damage to a battery attached to a DRAM when the bit-lines of the DRAM are activated, while minimizing the time to access digital data retain within the DRAM array. The decode circuit within a DRAM will receive a digital address word indicating column locations of a plurality of desired digital data bits retained within an array of DRAM memory cells, decode digital address word, and selectively activate bit-lines of said column locations of said plurality of desired digital data bits at a first time and activate all remaining bit-lines at times subsequent to the first time to minimize RAS cycle current. The decode circuit has a decode logic circuit to select one of the column locations that is designated by the digital address date word. The decode circuit additionally has a first timing circuit and at least one second timing circuit. The first timing circuit is connected between the decode logic circuit and the column locations of said array of DRAM cells to activate the selected one column location to be activated at the first time. At least one second timing circuit is connected between the logic circuit and the column locations of said DRAM cells to activate all unselected locations at times subsequent to the first time.

摘要翻译： 解码电路向DRAM提供定时和控制信号，以在行地址选通（RAS）周期期间在DRAM内的位线激活期间确保最小电流浪涌。 在RAS周期期间提供最小电流浪涌可防止当DRAM的位线被激活时对连接到DRAM的电池造成损坏，同时使访问数字数据的时间最小化保留在DRAM阵列内。 DRAM内的解码电路将接收指示保留在DRAM存储单元的阵列内的多个所需数字数据位的列位置的数字地址字，解码数字地址字，并选择性地激活所述多个存储单元的列位置的位线 的所需数字数据位，并且在第一次之后的时间激活所有剩余的位线，以使RAS周期电流最小化。 解码电路具有解码逻辑电路，用于选择由数字地址日期字指定的列位置之一。 解码电路还具有第一定时电路和至少一个第二定时电路。 第一定时电路连接在解码逻辑电路和所述DRAM单元阵列的列位置之间，以激活所选择的一个列位置以在第一时间被激活。 在逻辑电路和所述DRAM单元的列位置之间连接至少一个第二定时电路，以在第一次之后的时间激活所有未选择的位置。

公开(公告)号：US06434033B1

公开(公告)日：2002-08-13

申请号：US09726473

申请日：2000-11-30

申请人： Pien Chien

发明人： Pien Chien

IPC分类号： G11C1500

CPC分类号： G11C29/70 ,  G11C11/408 ,  G11C15/00 ,  G11C29/789 ,  G11C29/846

摘要： A DRAM module and a method of replacing a damaged DRAM cell in the DRAM module with a SRAM. The DRAM module has at least a non-volatile memory and a DRAM control logic circuit. In the process of replacing the damaged DRAM with the SRAM, the damaged address data is compared to DRAM address data. If the data are consistent, the address of the SRAM is used to access data. Meanwhile, the output enabling signal of the DRAM cell is turned off. It can thus assist the computer to correctly find the good DRAM cell for data access, so as to ensure a normal operation of the computer.

摘要翻译： DRAM模块和用SRAM替代DRAM模块中损坏的DRAM单元的方法。 DRAM模块至少具有非易失性存储器和DRAM控制逻辑电路。 在用SRAM替换损坏的DRAM的过程中，将损坏的地址数据与DRAM地址数据进行比较。 如果数据一致，则使用SRAM的地址来访问数据。 同时，关闭DRAM单元的输出使能信号。 因此，它可以帮助计算机正确找到用于数据访问的良好DRAM单元，以确保计算机的正常运行。

公开(公告)号：US06405331B1

公开(公告)日：2002-06-11

申请号：US09359448

申请日：1999-07-22

申请人： Pien Chien

发明人： Pien Chien

IPC分类号： G11C2900

CPC分类号： G11C29/12 ,  G11C29/48 ,  G11C2207/104

摘要： A method is provided for performing a BIST (built-in self test) procedure on embedded memory through a time-division multipexed scheme with a reduced number of probing pads. This method is characterized in the use of a time-division multipexed scheme to obtain the addresses of bad memory cells so that these address data can be used to indicate the locations of the bad memory cells during repair process. Moreover, this method is characterized in that it requires only a fewer number of probing pads than the prior art so that the required layout area for the BIST procedure can be reduced as compared to the prior art. This method is therefore more cost-effective to implement than the prior art.

摘要翻译： 提供了一种通过具有减少的探测焊盘数量的时分多重方案对嵌入式存储器执行BIST（内置自检）程序的方法。 该方法的特征在于使用时分多路复用方案来获得不良存储器单元的地址，使得这些地址数据可用于指示在修复过程中坏存储器单元的位置。 此外，该方法的特征在于，其仅需要比现有技术少的探测焊盘数量，因此与现有技术相比可以减少BIST过程所需的布局面积。 因此，该方法比现有技术更具成本效益。