公开(公告)号：US20130277685A1

公开(公告)日：2013-10-24

申请号：US13451696

申请日：2012-04-20

Applicant: Ken-Ichi GOTO ,  Dhanyakumar Mahaveer SATHAIYA ,  Ching-Chang WU ,  Tzer-Min SHEN

Inventor： Ken-Ichi GOTO ,  Dhanyakumar Mahaveer SATHAIYA ,  Ching-Chang WU ,  Tzer-Min SHEN

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A transistor structure with improved device performance, and a method for forming the same is provided. The transistor structure is an SOI (silicon-on-insulator) transistor. In one embodiment, a silicon layer over the oxide layer is a relatively uniform film and in another embodiment, the silicon layer over the oxide layer is a silicon fin. The transistor devices include source/drain structures formed of a strain material that extends through the silicon layer, through the oxide layer and into the underlying substrate which may be silicon. The source/drain structures also include portions that extend above the upper surface of the silicon layer thereby providing an increased volume of the strain layer to provide added carrier mobility and higher performance.

Abstract translation: 提供了具有改进的器件性能的晶体管结构及其形成方法。 晶体管结构是SOI（绝缘体上硅）晶体管。 在一个实施例中，氧化物层上的硅层是相对均匀的膜，在另一个实施例中，氧化物层上的硅层是硅片。 晶体管器件包括由延伸穿过硅层的应变材料形成的源极/漏极结构，穿过氧化物层并进入可能是硅的下面的衬底。 源极/漏极结构还包括在硅层的上表面上方延伸的部分，从而提供增加的应变层的体积以提供附加的载流子迁移率和更高的性能。

公开(公告)号：US20130265799A1

公开(公告)日：2013-10-10

申请号：US13477062

申请日：2012-05-22

Applicant: Wan-Li Chuang ,  Chien-Min Chang ,  Li-Jung Yu ,  Mei-Hsiung Tsai ,  Yung-Ching Chang ,  Ju-Chen Chiu

Inventor： Wan-Li Chuang ,  Chien-Min Chang ,  Li-Jung Yu ,  Mei-Hsiung Tsai ,  Yung-Ching Chang ,  Ju-Chen Chiu

IPC: F21V8/00

CPC classification number: H01H13/83 ,  G06F3/0202 ,  H01H2219/028 ,  H01H2219/056 ,  H01H2219/062 ,  H01H2229/008 ,  H01H2231/002

Abstract: An electronic device includes a display module, a base and a keyboard module. The display module is pivoted on the base. The keyboard module is disposed on the base. The keyboard module has a plurality of keys. Each of the keys includes a main body and an imprinted structure. The main body has a top surface. The imprinted structure is disposed on the top surface of the main body and includes a light guiding portion and a light scattering portion. A light emitted by the display module illuminates the keyboard module. The light is guided towards a specific direction when the light passes through the light guiding portion, and the light is scattered in other directions when the light passes through the light scattering portion.

Abstract translation: 电子设备包括显示模块，基座和键盘模块。 显示模块在基座上枢转。 键盘模块设置在基座上。 键盘模块具有多个键。 每个键包括主体和压印结构。 主体有一个顶面。 印刷结构设置在主体的顶面上，具有导光部和光散射部。 显示模块发出的光照亮键盘模块。 当光通过导光部分时，光被引向特定方向，并且当光通过光散射部分时，光在其它方向上散射。

公开(公告)号：USD688215S1

公开(公告)日：2013-08-20

申请号：US29440664

申请日：2012-12-25

Applicant: Tzu-Cheng Yu ,  Ching-Chang Ni ,  Hong-Xiu Luo ,  Ching-Tang Chin ,  Jia-Ke Huang

Designer： Tzu-Cheng Yu ,  Ching-Chang Ni ,  Hong-Xiu Luo ,  Ching-Tang Chin ,  Jia-Ke Huang

公开(公告)号：USD687786S1

公开(公告)日：2013-08-13

申请号：US29419228

申请日：2012-04-26

Applicant: Ching-Tang Chin ,  Ying-Chen Cheng ,  Hong-Xiu Luo ,  Ho-Chyuan Su ,  Ching-Chang Ni ,  Tzu-Cheng Yu

Designer： Ching-Tang Chin ,  Ying-Chen Cheng ,  Hong-Xiu Luo ,  Ho-Chyuan Su ,  Ching-Chang Ni ,  Tzu-Cheng Yu

公开(公告)号：US08507979B1

公开(公告)日：2013-08-13

申请号：US13563470

申请日：2012-07-31

Applicant: Yuan-Sheng Huang ,  Ming-Ching Chang ,  Chao-Cheng Chen

Inventor： Yuan-Sheng Huang ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L29/66

CPC classification number: H01L29/4966 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/78

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a semiconductor substrate and forming a gate trench therein. The method also includes filling in the gate trench partially with a work-function (WF) metal stack, and filling in the remaining gate trench with a dummy-filling-material (DFM) over the WF metal stack. A sub-gate trench is formed by etching-back the WF metal stack in the gate trench, and is filled with an insulator cap to form an isolation region in the gate trench. The DFM is fully removed to from a MG-center trench (MGCT) in the gate trench, which is filled with a fill metal.

Abstract translation: 公开了制造半导体集成电路（IC）的方法。 该方法包括提供半导体衬底并在其中形成栅极沟槽。 该方法还包括用工作功能（WF）金属堆叠部分地填充栅极沟槽，并且在WF金属堆叠上用虚拟填充材料（DFM）填充剩余的栅极沟槽。 通过蚀刻在栅极沟槽中的WF金属堆叠形成子栅极沟槽，并且填充有绝缘体帽以在栅极沟槽中形成隔离区域。 DFM从栅极沟槽中的MG-中心沟槽（MGCT）被完全去除，其填充有填充金属。

公开(公告)号：USD687391S1

公开(公告)日：2013-08-06

申请号：US29419229

申请日：2012-04-26

Applicant: Ming-Yu Cao ,  Tzu-Cheng Yu ,  Hsiao-Wen Tseng ,  Ching-Chang Ni ,  Hong-Xiu Luo ,  Ho-Chyuan Su

Designer： Ming-Yu Cao ,  Tzu-Cheng Yu ,  Hsiao-Wen Tseng ,  Ching-Chang Ni ,  Hong-Xiu Luo ,  Ho-Chyuan Su

公开(公告)号：US20130138499A1

公开(公告)日：2013-05-30

申请号：US13308386

申请日：2011-11-30

Applicant: Peter Henry Tu ,  Mark Lewis Grabb ,  Xiaoming Liu ,  Ting Yu ,  Yi Yao ,  Dashan Gao ,  Ming-Ching Chang

Inventor： Peter Henry Tu ,  Mark Lewis Grabb ,  Xiaoming Liu ,  Ting Yu ,  Yi Yao ,  Dashan Gao ,  Ming-Ching Chang

IPC: G06Q30/02

Abstract: An advertising system is disclosed. In one embodiment, the system includes an advertising display configured to provide an advertisement to potential customers and a camera configured to capture images of the potential customers when the potential customers pass the advertising display. The system may also include an image processing system having a processor and a memory. The memory may include application instructions for execution by the processor, and the image processing system may be configured to execute the application instructions to derive usage characteristics of the potential customers with respect to the advertising display through analysis of the captured images. Additional methods, systems, and articles of manufacture are also disclosed.

Abstract translation: 公开了广告系统。 在一个实施例中，系统包括被配置为向潜在客户提供广告的广告显示器和被配置为当潜在客户通过广告显示时捕获潜在客户的图像的照相机。 该系统还可以包括具有处理器和存储器的图像处理系统。 存储器可以包括用于由处理器执行的应用指令，并且图像处理系统可以被配置为执行应用指令以通过分析所捕获的图像来导出相对于广告显示的潜在客户的使用特性。 还公开了附加的方法，系统和制品。

公开(公告)号：US20130127433A1

公开(公告)日：2013-05-23

申请号：US13744037

申请日：2013-01-17

Applicant: Chan-Hong CHERN ,  Tzu Ching CHANG ,  Min-Shueh YUAN ,  Yuwen SWEI ,  Chih-Chang LIN ,  Chiang PU ,  Ming-Chieh HUANG ,  Kuoyuan HSU

Inventor： Chan-Hong CHERN ,  Tzu Ching CHANG ,  Min-Shueh YUAN ,  Yuwen SWEI ,  Chih-Chang LIN ,  Chiang PU ,  Ming-Chieh HUANG ,  Kuoyuan HSU

IPC: G05F1/44

CPC classification number: H02M3/158 ,  G05F1/44 ,  G05F1/56

Abstract: A method of operating a voltage regulator circuit includes generating a control signal by an amplifier of the voltage regulator circuit. The control signal is generated based on a reference signal at an inverting input of the amplifier and a feedback signal at a non-inverting input of the amplifier. A driving current flowing toward an output node of the voltage regulator circuit is generated by a driver responsive to the control signal, and the driver is coupled between a first power node and the output node. The feedback signal is generated responsive to a voltage level at the output node. A transistor, coupled between the output node and a second power node, is caused to operate in saturation mode during a period while the voltage regulator circuit is operating.

Abstract translation: 一种操作电压调节器电路的方法包括由稳压器电路的放大器产生控制信号。 控制信号基于放大器的反相输入处的参考信号和放大器的非反相输入端的反馈信号而产生。 通过响应于控制信号的驱动器产生朝向电压调节器电路的输出节点流动的驱动电流，并且驱动器耦合在第一功率节点和输出节点之间。 响应于输出节点处的电压电平产生反馈信号。 耦合在输出节点和第二功率节点之间的晶体管在电压调节器电路工作期间的一段时间内使其工作在饱和模式。

公开(公告)号：US20130029476A1

公开(公告)日：2013-01-31

申请号：US13540781

申请日：2012-07-03

Applicant: Chien-Sen WENG ,  Mong-Yeng Xing ,  Yu-Ching Chang ,  Wei-Chang Yu ,  Yao-Hui Lin

Inventor： Chien-Sen WENG ,  Mong-Yeng Xing ,  Yu-Ching Chang ,  Wei-Chang Yu ,  Yao-Hui Lin

IPC: H01L21/78

CPC classification number: B28D5/0011 ,  B28D5/0052 ,  Y02P80/30

Abstract: A dicing process is provided for cutting a wafer along a plurality of predetermined scribe lines into a plurality of dies that are releasably adhered to a release film. The dicing process includes: (a) disposing a wafer-breaking carrier on a supporting device, the wafer-breaking carrier having a chipping unit; (b) disposing the wafer above the supporting device such that the chipping unit is at a position corresponding to the scribe lines; and (c) adhering a release surface of the release film to the wafer by applying a force to the release film to contact the chipping unit of the wafer-breaking carrier with the wafer, such that the wafer is split along the scribe lines into the dies.

Abstract translation: 提供了一种切割工艺，用于沿着多条预定划线将晶片切割成可剥离地粘附到脱模膜上的多个模具。 切割工艺包括：（a）在支撑装置上设置晶片破坏载体，晶片断开载体具有切屑单元; （b）将所述晶片设置在所述支撑装置上方，使得所述切屑单元处于与所述划线对应的位置; 并且（c）通过向剥离膜施加力使脱模膜的释放表面附着到晶片上，以将晶片破坏载体的切屑单元与晶片接触，使得晶片沿着划线分裂成 死了

公开(公告)号：US08310940B2

公开(公告)日：2012-11-13

申请号：US12793643

申请日：2010-06-03

Applicant: Richard Earl Jones ,  Ching-Chang Liao ,  Daniel K. Chappell

Inventor： Richard Earl Jones ,  Ching-Chang Liao ,  Daniel K. Chappell

IPC: H04L12/28 ,  H04B3/46 ,  H04N7/173 ,  H04N17/00

CPC classification number: H04L12/2801 ,  H04L43/50

Abstract: In order to measure the performance of a DOCSIS upstream channel as well as to locate impairments, a special test signal is transmitted in a time slot of the upstream channel by a test instrument positioned anywhere within the CATV plant. A second test instrument, located at the termination point of the upstream plant, then detects, recovers, and processes the test signal in order to complete the measurement. The typical methods used to detect and recover bursted signals within a DOCSIS upstream channel use precise timing information transmitted in a corresponding DOCSIS downstream channel. Unfortunately, the downstream channel and thus the precise timing information are not always available to the secondary test instrument. The present invention also describes an apparatus and method for detecting a bursted test signal without the use of the DOCSIS upstream channel timing.

Abstract translation: 为了测量DOCSIS上行信道的性能以及定位损伤，通过位于CATV工厂内任何地方的测试仪器，在上游信道的时隙中发送特殊测试信号。 位于上游工厂终端的第二个测试仪器，然后检测，恢复和处理测试信号，以完成测量。 用于检测和恢复DOCSIS上行信道中的突发信号的典型方法使用在相应DOCSIS下行信道中发送的精确定时信息。 不幸的是，下游通道和精确的定时信息并不总是适用于二次测试仪器。 本发明还描述了一种用于在不使用DOCSIS上行信道定时的情况下检测突发测试信号的装置和方法。