公开(公告)号：US20070099402A1

公开(公告)日：2007-05-03

申请号：US11613462

申请日：2006-12-20

Applicant: Horng-Huei Tseng ,  Chung-Hu Ge ,  Chao-Hsiung Wang

Inventor： Horng-Huei Tseng ,  Chung-Hu Ge ,  Chao-Hsiung Wang

IPC: H01L21/20 ,  H01L21/36 ,  H01L21/66 ,  G01R31/26

CPC classification number: H01L23/544 ,  H01L21/67115 ,  H01L29/045 ,  H01L2223/54466 ,  H01L2223/54493 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A reliable semiconductor structure and its fabrication method. Active regions and/or scribe lines on a semiconductor substrate are configured along a crack resistant crystalline direction. Thermal cracking due to the abrupt temperature ramp of rapid thermal processing can be avoided.

Abstract translation: 可靠的半导体结构及其制造方法。 半导体衬底上的有源区和/或划线沿着耐裂纹结晶方向配置。 可以避免由于快速热处理的突然温度斜坡导致的热裂纹。

公开(公告)号：US07208754B2

公开(公告)日：2007-04-24

申请号：US11114981

申请日：2005-04-26

Applicant: Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu

Inventor： Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu

IPC: H01L29/06

CPC classification number: H01L29/0847 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842

Abstract: A semiconductor device includes a substrate, a first epitaxial layer, a second epitaxial layer, a third epitaxial layer, a first trench, and a second trench. The first epitaxial layer is formed on the substrate. The first layer has lattice mismatch relative to the substrate. The second epitaxial layer is formed on the first layer, and the second layer has lattice mismatch relative to the first layer. The third epitaxial layer is formed on the second layer, and the third layer has lattice mismatch relative to the second layer. Hence, the third layer may be strained silicon. The first trench extends through the first layer. The second trench extends through the third layer and at least partially through the second layer. At least part of the second trench is aligned with at least part of the first trench, and the second trench is at least partially filled with an insulating material.

Abstract translation: 半导体器件包括衬底，第一外延层，第二外延层，第三外延层，第一沟槽和第二沟槽。 第一外延层形成在基板上。 第一层相对于衬底具有晶格失配。 第二外延层形成在第一层上，第二层相对于第一层具有晶格失配。 第三外延层形成在第二层上，第三层相对于第二层具有晶格失配。 因此，第三层可以是应变硅。 第一沟槽延伸穿过第一层。 第二沟槽延伸穿过第三层并且至少部分地穿过第二层。 所述第二沟槽的至少一部分与所述第一沟槽的至少一部分对准，并且所述第二沟槽至少部分地填充有绝缘材料。

公开(公告)号：US20050285140A1

公开(公告)日：2005-12-29

申请号：US10875141

申请日：2004-06-23

Applicant: Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chung-Hu Ge

Inventor： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chung-Hu Ge

IPC: H01L21/762 ,  H01L21/8238 ,  H01L29/10 ,  H01L31/0328

CPC classification number: H01L21/823878 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/7846 ,  H01L29/7848

Abstract: A method and system is disclosed for forming an improved isolation structure for strained channel transistors. In one example, an isolation structure is formed comprising a trench filled with a nitrogen-containing liner and a gap filler. The nitrogen-containing liner enables the isolation structure to reduce compressive strain contribution to the channel region.

Abstract translation: 公开了用于形成用于应变通道晶体管的改进的隔离结构的方法和系统。 在一个示例中，形成包括填充有含氮衬里和间隙填料的沟槽的隔离结构。 含氮衬垫使隔离结构能够减小对通道区域的压应变贡献。

公开(公告)号：US20050236616A1

公开(公告)日：2005-10-27

申请号：US10831981

申请日：2004-04-26

Applicant: Horng-Huei Tseng ,  Chung-Hu Ge ,  Chao-Hsiung Wang

Inventor： Horng-Huei Tseng ,  Chung-Hu Ge ,  Chao-Hsiung Wang

IPC: H01L21/00 ,  H01L21/66 ,  H01L23/544 ,  H01L29/02 ,  H01L29/04

CPC classification number: H01L23/544 ,  H01L21/67115 ,  H01L29/045 ,  H01L2223/54466 ,  H01L2223/54493 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A reliable semiconductor structure and its fabrication method. Active regions and/or scribe lines on a semiconductor substrate are configured along a crack resistant crystalline direction. Thermal cracking due to the abrupt temperature ramp of rapid thermal processing can be avoided.

Abstract translation: 可靠的半导体结构及其制造方法。 半导体衬底上的有源区和/或划线沿着耐裂纹结晶方向配置。 可以避免由于快速热处理的突然温度斜坡导致的热裂纹。

公开(公告)号：US20050035426A1

公开(公告)日：2005-02-17

申请号：US10687377

申请日：2003-10-16

Applicant: Chih-Hsin Ko ,  Yee-Chia Yeo ,  Chung-Hu Ge ,  Wen-Chin Lee

Inventor： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Chung-Hu Ge ,  Wen-Chin Lee

IPC: H01L21/28 ,  H01L21/306 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/00 ,  H01L21/8238

CPC classification number: H01L21/28123 ,  H01L21/76232 ,  H01L21/823481 ,  H01L29/7833

Abstract: A semiconductor isolation trench includes a substrate and a trench formed therein. The trench is lined with a nitrogen-containing liner and filled with a dielectric material. The nitrogen-containing liner preferably contacts the active region of a device, such as a transistor, located adjacent to the trench.

公开(公告)号：US20050032321A1

公开(公告)日：2005-02-10

申请号：US10637351

申请日：2003-08-08

Applicant: Chien-Chao Huang ,  Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu ,  Carlos Diaz ,  Fu-Liang Yang

Inventor： Chien-Chao Huang ,  Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu ,  Carlos Diaz ,  Fu-Liang Yang

IPC: H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843

Abstract: A structure to improve carrier mobility of a MOS device in an integrated circuit. The structure comprises a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a conformal stress film covering the source region, the drain region, and the conductive gate. In addition, the structure may comprise a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a plurality of stress films covering the source region, the drain region, and the conductive gate. Moreover, the structure may comprise a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a spacer disposed adjacent to the conductive gate, the spacer having a width less than 550 angstroms; a stress film covering the source region, the drain region, the conductive gate, and the spacer.

Abstract translation: 一种提高集成电路中MOS器件的载流子迁移率的结构。 该结构包括含有源区和漏区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 覆盖源极区域，漏极区域和导电栅极的共形应力膜。 此外，该结构可以包括含有源极区和漏极区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 覆盖源极区域，漏极区域和导电栅极的多个应力膜。 此外，该结构可以包括含有源极区和漏极区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 间隔件设置成与导电栅极相邻，间隔物具有小于550埃的宽度; 覆盖源极区域，漏极区域，导电栅极和间隔物的应力膜。

公开(公告)号：US20050023576A1

公开(公告)日：2005-02-03

申请号：US10657616

申请日：2003-09-08

Applicant: Wen-Chin Lee ,  Chung-Hu Ge ,  Chenming Hu

Inventor： Wen-Chin Lee ,  Chung-Hu Ge ,  Chenming Hu

IPC: H01L21/20 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/76 ,  H01L31/062 ,  H01L31/119

CPC classification number: H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/76232 ,  H01L21/823412 ,  H01L29/1054 ,  H01L29/66651

Abstract: A semiconductor structure including a highly strained selective epitaxial top layer suitable for use in fabricating a strained channel transistor. The top layer is deposited on the uppermost of a series of one or more lower layers. The lattice of each layer is mismatched with the lattice of its subjacent layer by an amount not less than the lattice mismatch between the lowest layer of the series and a substrate on which it resides. A trench is formed in the uppermost series layer. The trench has rounded corners so that a dielectric material filling the trench conforms to the round corners. The rounded corners are produced by heating the uppermost series layer after trench formation.

Abstract translation: 包括适用于制造应变通道晶体管的高应变选择性外延顶层的半导体结构。 顶层沉积在一系列一个或多个下层的最上面。 每个层的晶格与其下层的晶格不匹配，其量不小于该系列的最低层与其所在的衬底之间的晶格失配。 沟槽形成在最上层的层中。 沟槽具有圆角，使得填充沟槽的电介质材料符合圆角。 通过在沟槽形成之后加热最上面的串联层来产生圆角。