公开(公告)号：US08569146B2

公开(公告)日：2013-10-29

申请号：US13013296

申请日：2011-01-25

申请人： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chung-Hu Ge

发明人： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chung-Hu Ge

IPC分类号： H01L21/76

CPC分类号： H01L21/823878 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/7846 ,  H01L29/7848

摘要： A method and system is disclosed for forming an improved isolation structure for strained channel transistors. In one example, an isolation structure is formed comprising a trench filled with a nitrogen-containing liner and a gap filler. The nitrogen-containing liner enables the isolation structure to reduce compressive strain contribution to the channel region.

摘要翻译： 公开了用于形成用于应变通道晶体管的改进的隔离结构的方法和系统。 在一个示例中，形成包括填充有含氮衬里和间隙填料的沟槽的隔离结构。 含氮衬垫使隔离结构能够减小对通道区域的压应变贡献。

公开(公告)号：US07183593B2

公开(公告)日：2007-02-27

申请号：US10745831

申请日：2003-12-24

申请人： Yee-Chia Yeo ,  Wen-Chin Lee ,  Chih-Hsin Ko ,  Chung-Hu Ge ,  Chun-Chieh Lin ,  Chenming Hu

发明人： Yee-Chia Yeo ,  Wen-Chin Lee ,  Chih-Hsin Ko ,  Chung-Hu Ge ,  Chun-Chieh Lin ,  Chenming Hu

IPC分类号： H01L29/86 ,  H01L29/205

CPC分类号： H01L27/0629 ,  H01L29/165 ,  H01L29/8605

摘要： A heterostructure resistor comprises a doped region formed in a portion of a semiconductor substrate, the substrate comprising a first semiconductor material having a first natural lattice constant. The doped region comprises a semiconductor layer overlying the semiconductor substrate. The semiconductor layer comprises a second semiconductor material with a second natural lattice constant.

摘要翻译： 异质结构电阻器包括形成在半导体衬底的一部分中的掺杂区域，该衬底包括具有第一自然晶格常数的第一半导体材料。 掺杂区域包括覆盖半导体衬底的半导体层。 半导体层包括具有第二自然晶格常数的第二半导体材料。

公开(公告)号：US06974755B2

公开(公告)日：2005-12-13

申请号：US10687377

申请日：2003-10-16

申请人： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Chung-Hu Ge ,  Wen-Chin Lee

发明人： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Chung-Hu Ge ,  Wen-Chin Lee

IPC分类号： H01L21/28 ,  H01L21/306 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/78

CPC分类号： H01L21/28123 ,  H01L21/76232 ,  H01L21/823481 ,  H01L29/7833

摘要： A semiconductor isolation trench includes a substrate and a trench formed therein. The trench is lined with a nitrogen-containing liner and filled with a dielectric material. The nitrogen-containing liner preferably contacts the active region of a device, such as a transistor, located adjacent to the trench.

摘要翻译： 半导体隔离沟槽包括衬底和形成在其中的沟槽。 沟槽衬有含氮衬里并填充介电材料。 优选地，所述含氮衬垫接触位于所述沟槽附近的诸如晶体管的器件的有源区。

公开(公告)号：US20070161206A1

公开(公告)日：2007-07-12

申请号：US11586936

申请日：2006-10-26

申请人： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chung-Hu Ge

发明人： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chung-Hu Ge

IPC分类号： H01L21/76

CPC分类号： H01L21/823878 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/7846 ,  H01L29/7848

摘要： A method and system is disclosed for forming an improved isolation structure for strained channel transistors. In one example, an isolation structure is formed comprising a trench filled with a nitrogen-containing liner and a gap filler. The nitrogen-containing liner enables the isolation structure to reduce compressive strain contribution to the channel region.

摘要翻译： 公开了用于形成用于应变通道晶体管的改进的隔离结构的方法和系统。 在一个示例中，形成包括填充有含氮衬里和间隙填料的沟槽的隔离结构。 含氮衬垫使隔离结构能够减小对通道区域的压应变贡献。

公开(公告)号：US20050285140A1

公开(公告)日：2005-12-29

申请号：US10875141

申请日：2004-06-23

申请人： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chung-Hu Ge

发明人： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chung-Hu Ge

IPC分类号： H01L21/762 ,  H01L21/8238 ,  H01L29/10 ,  H01L31/0328

CPC分类号： H01L21/823878 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/7846 ,  H01L29/7848

摘要： A method and system is disclosed for forming an improved isolation structure for strained channel transistors. In one example, an isolation structure is formed comprising a trench filled with a nitrogen-containing liner and a gap filler. The nitrogen-containing liner enables the isolation structure to reduce compressive strain contribution to the channel region.

摘要翻译： 公开了用于形成用于应变通道晶体管的改进的隔离结构的方法和系统。 在一个示例中，形成包括填充有含氮衬里和间隙填料的沟槽的隔离结构。 含氮衬垫使隔离结构能够减小对通道区域的压应变贡献。

公开(公告)号：US20050035426A1

公开(公告)日：2005-02-17

申请号：US10687377

申请日：2003-10-16

申请人： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Chung-Hu Ge ,  Wen-Chin Lee

发明人： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Chung-Hu Ge ,  Wen-Chin Lee

IPC分类号： H01L21/28 ,  H01L21/306 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/00 ,  H01L21/8238

CPC分类号： H01L21/28123 ,  H01L21/76232 ,  H01L21/823481 ,  H01L29/7833

摘要： A semiconductor isolation trench includes a substrate and a trench formed therein. The trench is lined with a nitrogen-containing liner and filled with a dielectric material. The nitrogen-containing liner preferably contacts the active region of a device, such as a transistor, located adjacent to the trench.

公开(公告)号：US07442967B2

公开(公告)日：2008-10-28

申请号：US11407633

申请日：2006-04-20

申请人： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chenming Hu

发明人： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chenming Hu

IPC分类号： H01L31/0328

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7848

摘要： A transistor includes a gate dielectric overlying a channel region. A source region and a drain region are located on opposing sides of the channel region. The channel region is formed from a first semiconductor material and the source and drain regions are formed from a second semiconductor material. A gate electrode overlies the gate dielectric. A pair of spacers is formed on sidewalls of the gate electrode. Each of the spacers includes a void adjacent the channel region. A high-stress film can overlie the gate electrode and spacers.

摘要翻译： 晶体管包括覆盖沟道区的栅极电介质。 源极区域和漏极区域位于沟道区域的相对侧上。 沟道区由第一半导体材料形成，源极和漏极区由第二半导体材料形成。 栅极电极覆盖栅极电介质。 在栅电极的侧壁上形成一对间隔物。 每个间隔件包括邻近通道区域的空隙。 高应力膜可以覆盖栅电极和间隔物。

公开(公告)号：US20060255365A1

公开(公告)日：2006-11-16

申请号：US11483913

申请日：2006-07-10

申请人： Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chun-Chieh Lin ,  Chenming Hu

发明人： Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chun-Chieh Lin ,  Chenming Hu

IPC分类号： H01L31/00

CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

摘要： A semiconductor chip includes a semiconductor substrate 126, in which first and second active regions are disposed. A resistor 124 is formed in the first active region and the resistor 124 includes a doped region 128 formed between two terminals 136. A strained channel transistor 132 is formed in the second active region. The transistor includes a first and second stressor 141, formed in the substrate oppositely adjacent a strained channel region 143.

公开(公告)号：US07112495B2

公开(公告)日：2006-09-26

申请号：US10729095

申请日：2003-12-05

申请人： Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chun-Chieh Lin ,  Chenming Hu

发明人： Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chun-Chieh Lin ,  Chenming Hu

IPC分类号： H01L21/336 ,  H01L21/76

CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

摘要： A semiconductor chip includes a semiconductor substrate 126, in which first and second active regions are disposed. A resistor 124 is formed in the first active region and the resistor 124 includes a doped region 128 formed between two terminals 136. A strained channel transistor 132 is formed in the second active region. The transistor includes a first and second stressor 141, formed in the substrate oppositely adjacent a strained channel region 143.

摘要翻译： 半导体芯片包括其中设置有第一和第二有源区的半导体衬底126。 电阻器124形成在第一有源区域中，并且电阻器124包括形成在两个端子136之间的掺杂区域128。 应变通道晶体管132形成在第二有源区中。 该晶体管包括第一和第二应力源141，该第一和第二应力器141形成在与基片相反的相邻的应变通道区域143之间。

公开(公告)号：US20060081928A1

公开(公告)日：2006-04-20

申请号：US10969374

申请日：2004-10-20

申请人： Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chung-Hu Ke

发明人： Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chung-Hu Ke

IPC分类号： H01L21/84 ,  H01L29/06

CPC分类号： H01L29/66772 ,  H01L27/1203 ,  H01L29/78618 ,  Y10S257/90

摘要： A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation spacer formed surrounding the semiconductor mesa and filling any undercut region at edges of the semiconductor mesa.