公开(公告)号：US5793995A

公开(公告)日：1998-08-11

申请号：US684486

申请日：1996-07-19

Applicant: Dwight D. Riley ,  David J. Maguire

Inventor： Dwight D. Riley ,  David J. Maguire

IPC: G06F13/40 ,  G06F13/00

CPC classification number: G06F13/4027

Abstract: The present invention relates to a system and method for shadowing data of a first register and a second register of a computer system that share a common address. When a bus agent runs a write operation to the register address, retry logic of a first bridge circuit retries the write operation and masks access by the bus agent to the bus. Retry bus master logic reruns the write operation, in response to which the second bridge circuit subtractively decodes the rerun write operation and transfers the data to the second register. The bus agent is then allowed to retry the initial write operation, in response to which the first bridge circuit positively decodes the retried write operation and transfers the data to the first register. Thus, coherency is preserved between the first and second registers.

Abstract translation: 本发明涉及一种用于对共享共同地址的计算机系统的第一寄存器和第二寄存器的数据进行阴影化的系统和方法。 当总线代理对寄存器地址执行写入操作时，第一桥接电路的重试逻辑重试写入操作，并掩盖总线代理对总线的访问。 重试总线主机逻辑重新执行写入操作，响应于此，第二桥接电路对该重新运行写入操作进行减法解码并将数据传送到第二寄存器。 然后允许总线代理重试初始写操作，响应于此，第一桥电路对其进行重试写入操作，并将数据传送到第一寄存器。 因此，在第一和第二寄存器之间保持一致性。

公开(公告)号：US20090037617A1

公开(公告)日：2009-02-05

申请号：US11932265

申请日：2007-10-31

Applicant: Dwight D. RILEY ,  James Xuan Dinh ,  Barry S. Basile ,  Kenneth A. Jansen ,  Hubert E. Brinkmann ,  David L. Matthews ,  Paul V. Brownell

Inventor： Dwight D. RILEY ,  James Xuan Dinh ,  Barry S. Basile ,  Kenneth A. Jansen ,  Hubert E. Brinkmann ,  David L. Matthews ,  Paul V. Brownell

IPC: G06F13/10 ,  G06F13/14

CPC classification number: G06F13/387

Abstract: A middle manager and methods are provided to enable a plurality of host devices to share one or more input/output devices. The middle manager initializes each shared input/output device and binds one or more functions of each input/output device to a specific host node in the system, such that hosts may only access functions to which they are bound. The middle manager may also utilize a configuration register map to translate values from the actual configuration register into a unique modified value for each of the plurality of host devices such that each host device may access and use the shared input/output device regardless of the firmware or operating system operating thereon.

Abstract translation: 提供中间管理器和方法以使得多个主机设备能够共享一个或多个输入/输出设备。 中间管理器初始化每个共享输入/输出设备，并将每个输入/输出设备的一个或多个功能绑定到系统中的特定主机节点，使得主机只能访问它们所绑定的功能。 中间管理器还可以使用配置寄存器映射来将实际配置寄存器中的值转换为多个主机设备中的每一个的唯一修改值，使得每个主机设备可访问和使用共享输入/输出设备，而不管固件如何 或在其上操作的操作系统。

公开(公告)号：US20090037609A1

公开(公告)日：2009-02-05

申请号：US11830747

申请日：2007-07-30

Applicant: Dwight D. Riley ,  James X. Dinh ,  Barry S. Basile ,  Kenneth A. Jansen ,  Hubert E. Brinkmann ,  David L. Matthews ,  Paul V. Brownell

Inventor： Dwight D. Riley ,  James X. Dinh ,  Barry S. Basile ,  Kenneth A. Jansen ,  Hubert E. Brinkmann ,  David L. Matthews ,  Paul V. Brownell

IPC: G06F3/00

CPC classification number: G06F3/0227

Abstract: A middle manager and methods are provided to enable a plurality of host devices to share one or more input/output devices. The middle manager initializes each shared input/output device and binds one or more functions of each input/output device to a specific host node in the system, such that hosts may only access functions to which they are bound. The middle manager may also utilize a configuration register map to translate values from the actual configuration register into a unique modified value for each of the plurality of host devices such that each host device may access and use the shared input/output device regardless of the firmware or operating system operating thereon.

公开(公告)号：US20090010159A1

公开(公告)日：2009-01-08

申请号：US11825492

申请日：2007-07-06

Applicant: Paul V. Brownell ,  David L. Matthews ,  James Xuan Dinh ,  Hubert E. Brinkmann ,  Dwight D. Riley ,  Hahn Vo Norden ,  Kenneth T. Chin

Inventor： Paul V. Brownell ,  David L. Matthews ,  James Xuan Dinh ,  Hubert E. Brinkmann ,  Dwight D. Riley ,  Hahn Vo Norden ,  Kenneth T. Chin

IPC: H04L12/26

CPC classification number: H04L47/263 ,  H04L41/08 ,  H04L47/18 ,  H04L47/215 ,  H04L47/30 ,  H04L47/39 ,  H04L2212/00

Abstract: A network node within a network includes a first receive buffer, first buffer management, a second receive buffer and second buffer management. The first buffer management performs link level credit based flow control for network packets that the first buffer management places in the first receive buffer. The second buffer management performs end-to-end credit based flow control for network packets that the second buffer management receives from the first receive buffer and processes before placing data in the second receive buffer.

Abstract translation: 网络内的网络节点包括第一接收缓冲器，第一缓冲器管理，第二接收缓冲器和第二缓冲器管理。 第一缓冲器管理对第一缓冲器管理放置在第一接收缓冲器中的网络分组执行基于链路级信用的流量控制。 第二缓冲器管理对第二缓冲器管理从第一接收缓冲器接收的网络分组执行基于端到端的信用流量控制，并且在将数据置于第二接收缓冲器之前进行处理。

公开(公告)号：US07447975B2

公开(公告)日：2008-11-04

申请号：US10243995

申请日：2002-09-12

Applicant: Dwight D. Riley

Inventor： Dwight D. Riley

IPC: H03M13/00

CPC classification number: G06F11/10 ,  H03M13/09

Abstract: A cyclic redundancy check (CRC) mechanism for the extensions (PCI-X) to the Peripheral Component Interconnect (PCI) bus system used in computer systems is fully backward compatible with the full PCI-X protocol. CRC check-bits are inserted to provide error detection capability for the header address and attribute phases, and for burst and DWORD transaction data phases. The CRC check-bits are inserted into unused attribute or clock (or target response) phases, or into reserved or reserved drive high portions (bits) of the address/data (AD), command/byte enable (C/BE#), or into the parity lanes of the PCI-X phases.

Abstract translation: 用于计算机系统中使用的外围组件互连（PCI）总线系统的扩展（PCI-X）的循环冗余校验（CRC）机制与完整的PCI-X协议完全向后兼容。 插入CRC校验位以提供头部地址和属性阶段以及突发和DWORD事务数据阶段的错误检测能力。 CRC校验位被插入到未使用的属性或时钟（或目标响应）阶段中，或者被插入到地址/数据（AD），命令/字节使能（C / BE＃）的预留或保留的驱动器高部分（位） 或进入PCI-X阶段的奇偶通道。

公开(公告)号：US07096306B2

公开(公告)日：2006-08-22

申请号：US10209846

申请日：2002-07-31

Applicant: Dwight D. Riley

Inventor： Dwight D. Riley

IPC: G06F13/20 ,  G06F13/36

CPC classification number: G06F15/17375

Abstract: An aliasing technique allows transparently connecting multiple interconnects across a shared cross-connect interconnect, allowing devices on one interconnect to communicate with devices on another interconnect as if both interconnects were connected by a single interconnect bridge. Each interconnect appears to the cross-connect interconnect as a device on the cross-connect interconnect. Transactions between devices on different interconnects are aliased by a routing engine connected to the cross-connect interconnect for transmittal across the cross-connect interconnect and are invisible to other transactions on the cross-connect interconnect. Transactions between devices on the same interconnect are invisible to other interconnects. Cache coherent requests are supported by the use of additional attribute bits.

Abstract translation: 混叠技术允许跨共享的交叉连接互连透明地连接多个互连，允许一个互连上的设备与另一个互连上的设备进行通信，就好像两个互连通过单个互连桥连接。 每个互连在交叉连接互连上显示为交叉连接互连上的设备。 不同互连设备之间的事务由连接到交叉连接互连的路由引擎进行混叠，以跨越交叉连接互连传输，并且对于交叉连接互连上的其他事务是不可见的。 在相同互连上的设备之间的事务对于其他互连是不可见的。 通过使用附加属性位来支持缓存一致请求。

公开(公告)号：US06449677B1

公开(公告)日：2002-09-10

申请号：US09266356

申请日：1999-03-11

Applicant: Sompong Paul Olarig ,  Thomas R. Seeman ,  Kenneth Jansen ,  Dwight D. Riley

Inventor： Sompong Paul Olarig ,  Thomas R. Seeman ,  Kenneth Jansen ,  Dwight D. Riley

IPC: G06F1338

CPC classification number: G06F13/105

Abstract: A high speed connection apparatus, method, and system is provided for peripheral components on digital computer systems. The peripheral component interconnect (PCI) specification is used as a baseline for an extended set of commands and attributes. The extended command and the attribute are issued on the bus during the clock cycle immediately after the clock cycle when the initial command was issued. The extended commands and attributes utilize the standard pin connections of conventional PCI devices and buses making the present invention backward-compatible with existing (conventional) PCI devices and legacy computer systems. Alternate embodiments of the present invention utilize a side-band address port (SBA port) to enable multiple targets to receive the same set of data. The conventional PCI command encoding is modified and the extended command is used to qualify the type of transaction and the attributes being used by the initiator of the transaction. Some extended command encodings are reserved but can be assigned in the future to new extended commands that will behave in a predictable manner with current devices.

Abstract translation: 为数字计算机系统上的外围组件提供高速连接装置，方法和系统。 外围组件互连（PCI）规范用作扩展命令和属性集的基准。 扩展命令和属性在发出初始命令的时钟周期之后的时钟周期内在总线上发出。 扩展的命令和属性利用常规PCI设备和总线的标准引脚连接，使本发明与现有（常规）PCI设备和传统计算机系统向后兼容。 本发明的替代实施例利用边带地址端口（SBA端口）使多个目标能够接收相同的数据集。 传统的PCI命令编码被修改，扩展命令用于限定事务类型和事务发起者使用的属性。 一些扩展的命令编码被保留，但可以将来分配给新的扩展命令，该扩展命令将以可预测的方式与当前设备一起运行。

公开(公告)号：US5774680A

公开(公告)日：1998-06-30

申请号：US570394

申请日：1995-12-11

Applicant: Christopher C. Wanner ,  Jeffrey C. Stevens ,  Robert A. Lester ,  Dwight D. Riley ,  David J. Maguire ,  James Edwards

Inventor： Christopher C. Wanner ,  Jeffrey C. Stevens ,  Robert A. Lester ,  Dwight D. Riley ,  David J. Maguire ,  James Edwards

IPC: G06F13/12 ,  G06F13/28 ,  G06F13/00

CPC classification number: G06F13/28 ,  G06F13/126

Abstract: A computer system having separate, yet compatible DMA controllers on a bus. Each DMA controller for controlling at least one DMA channel, each DMA controller having an independent set of registers for performing DMA operations and a configuration register for indicating channel status and designation. A DMA master for compatibly communicating with a processor and for initializing and communicating with the multiple DMA controllers.

公开(公告)号：US09037768B2

公开(公告)日：2015-05-19

申请号：US12937685

申请日：2008-04-28

Applicant: Hubert E. Brinkmann ,  Paul V. Brownell ,  David L. Matthews ,  Dwight D. Riley

Inventor： Hubert E. Brinkmann ,  Paul V. Brownell ,  David L. Matthews ,  Dwight D. Riley

IPC: G06F13/24 ,  G06F9/455

CPC classification number: G06F13/24 ,  G06F9/45558 ,  G06F2009/45579 ,  G06F2213/0026

Abstract: Embodiments of the present invention are directed to methods for virtualizing interrupt modes on behalf of interrupt-generating devices, including I/O-device controllers, so that newer interrupt-generating devices that lack older interrupt modes can be used in systems that continue to rely on older interrupt modes. In one embodiment of the present invention, a PCIe switch or PCIe-based host bridge is modified, or a new component introduced, to provide an interrupt-mode virtualizing function, or virtual interrupt-mode interface, that provides a virtual interrupt mode on behalf of interrupt-generating devices, such as I/O-device controllers, to operating systems, BIOS layers, and other components that communicate with the I/O-device controllers.

Abstract translation: 本发明的实施例涉及用于代表包括I / O设备控制器的中断产生设备虚拟化中断模式的方法，使得缺少较旧的中断模式的较新的中断产生设备可以在继续依赖的系统中使用 在较老的中断模式下。 在本发明的一个实施例中，改进了PCIe交换机或基于PCIe的主桥，或者引入了新的组件来提供代表虚拟中断模式的中断模式虚拟化功能或虚拟中断模式接口 诸如I / O设备控制器的中断产生设备到操作系统，BIOS层以及与I / O设备控制器通信的其他组件。

公开(公告)号：US08224987B2

公开(公告)日：2012-07-17

申请号：US11078851

申请日：2005-03-11

Applicant: Dwight D. Riley

Inventor： Dwight D. Riley

IPC: G06F15/173

CPC classification number: H04L12/28

Abstract: A system and method for a hierarchical interconnect network. Some illustrative embodiments comprise a network switch comprising a plurality of ports each adapted to couple to other devices external to the network switch as part of an interconnect network (the interconnect network comprises an inverted tree structure that originates with a root bus), a controller coupled to the plurality of ports (the controller defines an active path through the network switch, the active path follows the inverted tree structure), and a memory coupled to the controller (the memory comprising routing information). The controller uses the routing information to identify an alternate path through the network switch. At least part of the alternate path does not follow the inverted tree structure.

Abstract translation: 一种用于分层互连网络的系统和方法。 一些说明性实施例包括网络交换机，其包括多个端口，每个端口适于耦合到作为互连网络的一部分的网络交换机外部的其他设备（互连网络包括由根总线发起的反向树结构），控制器耦合 （控制器定义通过网络交换机的活动路径，主动路径遵循反向树结构），以及耦合到控制器（存储器包括路由信息）的存储器。 控制器使用路由信息来标识通过网络交换机的备用路径。 备用路径的至少一部分不遵循反向树结构。