Backside illuminated image sensor with reduced dark current
    21.
    发明授权
    Backside illuminated image sensor with reduced dark current 有权
    具有减少暗电流的背面照明图像传感器

    公开(公告)号:US07915067B2

    公开(公告)日:2011-03-29

    申请号:US12169723

    申请日:2008-07-09

    IPC分类号: H01L21/383

    摘要: A backside illuminated image sensor comprises a sensor layer implementing a plurality of photosensitive elements of a pixel array, and an oxide layer adjacent a backside surface of the sensor layer. The sensor layer comprises a seed layer and an epitaxial layer formed over the seed layer, with the seed layer having a cross-sectional doping profile in which a designated dopant is substantially confined to a pixel array area of the sensor layer. The doping profile advantageously reduces dark current generated at an interface between the sensor layer and the oxide layer. The image sensor may be implemented in a digital camera or other type of digital imaging device.

    摘要翻译: 背面照明图像传感器包括实现像素阵列的多个感光元件的传感器层和邻近传感器层的背面的氧化物层。 传感器层包括种子层和形成在种子层上的外延层,种子层具有横截面掺杂分布,其中指定的掺杂剂基本上限制在传感器层的像素阵列区域。 掺杂分布有利地减少了在传感器层和氧化物层之间的界面处产生的暗电流。 图像传感器可以在数字照相机或其他类型的数字成像装置中实现。

    Apparatus and method for manufacturing a semiconductor circuit
    22.
    发明授权
    Apparatus and method for manufacturing a semiconductor circuit 有权
    用于制造半导体电路的装置和方法

    公开(公告)号:US06762128B2

    公开(公告)日:2004-07-13

    申请号:US10177915

    申请日:2002-06-20

    IPC分类号: H01L21302

    摘要: A method and an apparatus for manufacturing, via a single fabrication line, circuits that are radiation tolerant and also circuits that are radiation intolerant. When production calls for radiation-tolerant circuits, low-pressure chemical vapor deposition is advantageously used to deposit an electrically-insulating material, such as silicon dioxide, in trenches to provide electrical isolation between adjacent semiconductor devices. When production requires radiation-intolerant circuits, as may be required for export, then the trenches are filled via a procedure that deposits an electrically-insulating material that, on exposure to ionizing radiation, generates a suitably large amount of “positive charge traps.” One procedure suitable for creating such positive charge traps is high-density plasma chemical vapor deposition (HDPCVD).

    摘要翻译: 一种用于通过单个制造线制造耐辐射电路以及辐射不耐受的电路的方法和装置。 当生产要求耐辐射电路时,低压化学气相沉积有利地用于在沟槽中沉积诸如二氧化硅的电绝缘材料,以在相邻的半导体器件之间提供电隔离。 当生产需要耐辐射电路时,可能需要输出电路,然后通过沉积电绝缘材料的程序来填充沟槽,这些电绝缘材料在暴露于电离辐射时产生适当大量的“正电荷陷阱”。 适用于产生这种正电荷陷阱的一种方法是高密度等离子体化学气相沉积(HDPCVD)。

    Electrostatic discharge protection for silicon-on-insulator
    23.
    发明授权
    Electrostatic discharge protection for silicon-on-insulator 失效
    绝缘体上硅的静电放电保护

    公开(公告)号:US6034399A

    公开(公告)日:2000-03-07

    申请号:US812183

    申请日:1997-03-06

    摘要: An ESD protection arrangement for a silicon-on-insulator device has an N-well type implant in the silicon substrate of the device, a p.sup.+ implant forming a juncture with the N-well type implant, and an n.sup.+ implant defining a juncture with the N-well type implant, in order to protect against negative transients and positive transients. At the p-channel threshold adjust, both the p-channel of the device and the N-well are implanted. Implanting the N-well to a depth of about 0.15 to about 0.30 .mu.m provides suitable characteristics for both the N-well and the p-channel.

    摘要翻译: 用于绝缘体上硅器件的ESD保护装置在器件的硅衬底中具有N阱型注入,形成与N阱型注入物的接合部的p +注入,以及限定具有与N阱注入的接合部的n + N阱型植入物,以防止负瞬变和正瞬变。 在p沟道阈值调整时,器件的p沟道和N阱都被植入。 将N阱植入约0.15至约0.30μm的深度为N阱和p沟道两者提供了合适的特性。

    Method to prevent latch-up and improve breakdown volatge in SOI mosfets
    24.
    发明授权
    Method to prevent latch-up and improve breakdown volatge in SOI mosfets 失效
    防止闩锁并改善SOI mosfets中击穿电压的方法

    公开(公告)号:US5527724A

    公开(公告)日:1996-06-18

    申请号:US304639

    申请日:1994-09-12

    摘要: SOI (silicon-on-insulator) technology has been touted as a promising approach for fabricating advanced integrated circuits because of its advantage over bulk silicon circuits such as faster speed and improved radiation tolerance. One drawback to SOI is that parasitic bipolar induced latch-up/breakdown voltage levels severely limits the maximum supply voltage at which SOI circuits and devices can operate. When the parasitic device turns on, the SOI transistor cannot be switched off by changing the gate bias. What is described is a method whereby the operating voltage in which this effect occurs is significantly increased thus allowing circuit operation at reasonable power supply voltages. The method is to implant an electrically neutral in silicon impurity atom such as krypton, xenon or germanium into the device to form ion scattering centers. The size of the impurity atom must be much larger than the size of the silicon atom. The size difference generating a scattering center.

    摘要翻译: SOI(绝缘体上硅)技术已经被吹捧为制造先进集成电路的有希望的方法,因为其优于体硅电路,例如更快的速度和更好的辐射耐受性。 SOI的一个缺点是寄生双极性引发的闭锁/击穿电压电平严重限制了SOI电路和器件可以工作的最大电源电压。 当寄生器件导通时,通过改变栅极偏置,不能关闭SOI晶体管。 所描述的是一种方法,其中发生该效应的工作电压显着增加,从而允许在合理的电源电压下进行电路操作。 该方法是在诸如氪,氙或锗之类的硅杂质原子中注入电中性以形成离子散射中心。 杂质原子的大小必须远大于硅原子的大小。 产生散射中心的尺寸差异。

    Wafer level processing for backside illuminated image sensors
    25.
    发明授权
    Wafer level processing for backside illuminated image sensors 有权
    背面照明图像传感器的晶片级处理

    公开(公告)号:US08119435B2

    公开(公告)日:2012-02-21

    申请号:US12940133

    申请日:2010-11-05

    IPC分类号: H01L21/00

    摘要: A backside illuminated image sensor comprises a sensor layer having a plurality of photosensitive elements of a pixel array, an oxide layer adjacent a backside surface of the sensor layer, and at least one dielectric layer adjacent a frontside surface of the sensor layer. A color filter array is formed on a backside surface of the oxide layer, and a transparent cover is attached to the backside surface of the oxide layer overlying the color filter array. Redistribution metal conductors are in electrical contact with respective bond pad conductors through respective openings in the dielectric layer. A redistribution passivation layer is formed over the redistribution metal conductors, and contact metallizations are in electrical contact with respective ones of the respective redistribution metal conductors through respective openings in the redistribution passivation layer. The image sensor may be implemented in a digital camera or other type of digital imaging device.

    摘要翻译: 背面照明图像传感器包括传感器层,其具有多个像素阵列的感光元件,邻近传感器层的背面的氧化物层以及与传感器层的前侧表面相邻的至少一个电介质层。 在氧化物层的背面形成有滤色器阵列,在覆盖滤色器阵列的氧化物层的背面附着有透明盖。 再分布金属导体通过介电层中的相应开口与相应的接合焊盘导体电接触。 再分布钝化层形成在再分布金属导体上,并且接触金属化通过再分布钝化层中的相应开口与相应的再分布金属导体中的相应的一个电接触。 图像传感器可以在数字照相机或其他类型的数字成像装置中实现。

    COLOR FILTER ARRAY ALIGNMENT MARK FORMATION IN BACKSIDE ILLUMINATED IMAGE SENSORS
    26.
    发明申请
    COLOR FILTER ARRAY ALIGNMENT MARK FORMATION IN BACKSIDE ILLUMINATED IMAGE SENSORS 审中-公开
    背景照明图像传感器中的颜色过滤器阵列对准标记形成

    公开(公告)号:US20110285880A1

    公开(公告)日:2011-11-24

    申请号:US13194593

    申请日:2011-07-29

    IPC分类号: H04N9/04 H01L31/0232

    摘要: A backside illuminated image sensor includes a sensor layer comprising photosensitive elements of the pixel array, an epitaxial layer formed on a frontside surface of the sensor layer, and a color filter array formed on a backside surface of the sensor layer. The epitaxial layer comprises polysilicon color filter array alignment marks formed in locations corresponding to respective color filter array alignment mark openings in the frontside surface of the sensor layer. The color filter array is aligned to the color filter array alignment marks of the epitaxial layer. The image sensor may be implemented in a digital camera or other type of digital imaging device.

    摘要翻译: 背面照明图像传感器包括包含像素阵列的感光元件的传感器层,形成在传感器层的前侧表面上的外延层和形成在传感器层的背面上的滤色器阵列。 外延层包括在与传感器层的前侧表面中的各个滤色器阵列对准标记开口对应的位置处形成的多晶硅滤色器阵列对准标记。 滤色器阵列与外延层的滤色器阵列对准标记对准。 图像传感器可以在数字照相机或其他类型的数字成像装置中实现。

    BACKSIDE ILLUMINATED IMAGE SENSOR WITH REDUCED DARK CURRENT
    27.
    发明申请
    BACKSIDE ILLUMINATED IMAGE SENSOR WITH REDUCED DARK CURRENT 审中-公开
    背光照明图像传感器,具有降低的电流

    公开(公告)号:US20110115957A1

    公开(公告)日:2011-05-19

    申请号:US13012843

    申请日:2011-01-25

    IPC分类号: H04N5/335 H01L31/14

    摘要: A backside illuminated image sensor comprises a sensor layer implementing a plurality of photosensitive elements of a pixel array, and an oxide layer adjacent a backside surface of the sensor layer. The sensor layer comprises a seed layer and an epitaxial layer formed over the seed layer, with the seed layer having a cross-sectional doping profile in which a designated dopant is substantially confined to a pixel array area of the sensor layer. The doping profile advantageously reduces dark current generated at an interface between the sensor layer and the oxide layer. The image sensor may be implemented in a digital camera or other type of digital imaging device.

    摘要翻译: 背面照明图像传感器包括实现像素阵列的多个感光元件的传感器层和邻近传感器层的背面的氧化物层。 传感器层包括种子层和形成在种子层上的外延层,种子层具有横截面掺杂分布,其中指定的掺杂剂基本上限制在传感器层的像素阵列区域。 掺杂分布有利地减少了在传感器层和氧化物层之间的界面处产生的暗电流。 图像传感器可以在数字照相机或其他类型的数字成像装置中实现。

    COLOR FILTER ARRAY ALIGNMENT MARK FORMATION IN BACKSIDE ILLUMINATED IMAGE SENSORS
    28.
    发明申请
    COLOR FILTER ARRAY ALIGNMENT MARK FORMATION IN BACKSIDE ILLUMINATED IMAGE SENSORS 有权
    背景照明图像传感器中的颜色过滤器阵列对准标记形成

    公开(公告)号:US20100006909A1

    公开(公告)日:2010-01-14

    申请号:US12169709

    申请日:2008-07-09

    IPC分类号: H01L31/00 H01L21/00

    摘要: A backside illuminated image sensor includes a sensor layer comprising photosensitive elements of the pixel array, an epitaxial layer formed on a frontside surface of the sensor layer, and a color filter array formed on a backside surface of the sensor layer. The epitaxial layer comprises polysilicon color filter array alignment marks formed in locations corresponding to respective color filter array alignment mark openings in the frontside surface of the sensor layer. The color filter array is aligned to the color filter array alignment marks of the epitaxial layer. The image sensor may be implemented in a digital camera or other type of digital imaging device.

    摘要翻译: 背面照明图像传感器包括包含像素阵列的感光元件的传感器层,形成在传感器层的前侧表面上的外延层和形成在传感器层的背面上的滤色器阵列。 外延层包括在与传感器层的前侧表面中的各个滤色器阵列对准标记开口对应的位置处形成的多晶硅滤色器阵列对准标记。 滤色器阵列与外延层的滤色器阵列对准标记对准。 图像传感器可以在数字照相机或其他类型的数字成像装置中实现。

    Semiconductor circuit having increased susceptibility to ionizing radiation
    29.
    发明授权
    Semiconductor circuit having increased susceptibility to ionizing radiation 有权
    半导体电路对电离辐射的敏感性增加

    公开(公告)号:US06665161B1

    公开(公告)日:2003-12-16

    申请号:US09592473

    申请日:2000-06-09

    IPC分类号: G05F140

    摘要: A radiation-susceptible integrated circuit comprises radiation sensor, a differential amplifier and circuit disabler. The radiation sensor includes two devices that have a different tolerance to ionizing radiation. When exposed to a total dose of ionizing radiation that exceeds the radiation tolerance of one of the devices but not the other, only the more radiation-susceptible device will exhibit an increase in leakage current. The differential amplifier is operable to generate an output signal having a value that is indicative of a difference or offset that exists between the output of the two devices. The output signal from the differential amplifier is received by the circuit disabler, which is activated, or not, as a function of the value of the output signal.

    摘要翻译: 辐射敏感集成电路包括辐射传感器,差分放大器和电路消除器。 辐射传感器包括对电离辐射具有不同容限的两个装置。 当暴露于超过其中一个装置而不是另一装置的辐射耐受性的电离辐射的总剂量时,只有更多的辐射敏感装置将表现出泄漏电流的增加。 差分放大器可操作以产生具有指示存在于两个器件的输出之间的差异或偏移的值的输出信号。 来自差分放大器的输出信号由作为输出信号的值的函数的电路消除器被接收,该电路被禁用或不被激活。

    Radiation hardened silicon-on-insulator (SOI) transistor having a body contact

    公开(公告)号:US06399989B1

    公开(公告)日:2002-06-04

    申请号:US09630216

    申请日:2000-08-01

    IPC分类号: H01L2701

    摘要: A radiation hardened silicon-on-insulator transistor is disclosed. A dielectric layer is disposed on a substrate, and a transistor structure is disposed on the dielectric layer. The transistor structure includes a body region, a source region, a drain region, and a gate layer. The body region is formed on a first surface portion of the dielectric layer, the source region is formed on a second surface portion of the dielectric layer contiguous with the first surface portion, the drain region is formed on a third surface portion of the dielectric layer contiguous with the first surface portion, and the gate layer overlies the body region and being operative to induce a channel in that portion of the body region disposed between and adjoining the source region and the drain region. In addition, multiple diffusions are placed across two edges of the source region. These diffusions are ohmically connected to the body region via a body contact, and these diffusions are also connected to the source region by a self-aligned salicide.