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    Single-ended to differential converter with relaxed common-mode input requirements
    22.
    发明授权
    Single-ended to differential converter with relaxed common-mode input requirements 失效
    单端到差分转换器，具有轻松的共模输入要求

    公开(公告)号：US5614864A

    公开(公告)日：1997-03-25

    申请号：US536405

    申请日：1995-09-29

    Applicant: Frederic M. Stubbe ,  Daryush Shamlou ,  Kashif A. Ahmed ,  Guangming Yin

    Inventor： Frederic M. Stubbe ,  Daryush Shamlou ,  Kashif A. Ahmed ,  Guangming Yin

    IPC: H03F3/45

    CPC classification number: H03F3/45475 ,  H03F3/45932 ,  H03F2203/45528

    Abstract: A converter for converting a single-ended input V.sub.IN to a differential output signal V.sub.OUT through positive and negative output terminals is disclosed. The converter comprises a fully differential amplifier with one of its input terminals coupled to the single-ended input and its other input terminal coupled to a fixed voltage. The converter also has a first resistor ("R.sub.1 ") coupled between the single-ended input and the positive input terminal of the fully differential amplifier, a second resistor ("R.sub.2 ") coupled between the fixed voltage and the negative input terminal of the fully differential amplifier, a third resistor ("R.sub.3 ") coupled between the positive input terminal and the negative output terminal of the fully differential amplifier, and a fourth resistor ("R.sub.4 ") coupled between the negative input terminal and the positive output terminal, wherein the values of such resistors are governed by: ##EQU1## The same principles can be applied to differential-to-single-ended converters as well.

    Abstract translation: 公开了一种通过正和负输出端将单端输入VIN转换为差分输出信号VOUT的转换器。 该转换器包括全差分放大器，其一个输入端耦合到单端输入端，其另一输入端耦合到一固定电压。 转换器还具有耦合在全差分放大器的单端输入端和正输入端之间的第一电阻（“R1”），耦合在固定电压和负输入端之间的第二电阻（“R2”） 全差分放大器，耦合在全差分放大器的正输入端和负输出端之间的第三电阻（“R3”）和耦合在负输入端和正输出端之间的第四电阻（“R4”）， 其中这些电阻的值由以下控制：相同的原理也可应用于差分到单端转换器。

    SIGNAL DELAY STRUCTURE IN HIGH SPEED BIT STREAM DEMULTIPLEXER
    24.
    发明申请
    SIGNAL DELAY STRUCTURE IN HIGH SPEED BIT STREAM DEMULTIPLEXER 有权
    信号延迟结构在高速位流解复用器

    公开(公告)号：US20100054384A1

    公开(公告)日：2010-03-04

    申请号：US12613740

    申请日：2009-11-06

    Applicant: Jun Cao ,  Guangming Yin

    Inventor： Jun Cao ,  Guangming Yin

    IPC: H04L7/00

    CPC classification number: G06F1/10 ,  H03K5/135 ,  H04J3/0629 ,  H04L7/0008 ,  H04L25/14

    Abstract: A signal delay structure and method of reducing skew between clock and data signals in a high-speed serial communications interface includes making a global adjustment to the clock signal in the time domain to compensate for a component of the skew that is common between the clock and all data signals. This can include skew caused by the variation in frequency of the input clock from a nominal value, misalignment between the phase of the clock and data generated at the source of the two signals. The global adjustment is made through a delay component that is common to all of the clock signal lines for which skew with data signals is to be compensated. A second level adjustment is made that compensates for the component of the skew that is common to the clock and a subset of the data signals.

    Abstract translation: 在高速串行通信接口中减少时钟和数据信号之间的偏差的信号延迟结构和方法包括对时域中的时钟信号进行全局调整，以补偿时钟和 所有数据信号。 这可能包括由输入时钟从标称值的频率变化引起的偏斜，时钟相位与在两个信号的源极产生的数据之间的偏移。 通过延迟分量进行全局调整，该延迟分量对于要对其进行补偿的具有数据信号的偏斜的所有时钟信号线是共同的。 进行第二级调整，补偿时钟共同的偏斜分量和数据信号的子集。

    System and method for testing the operation of a DLL-based interface
    25.
    发明授权
    System and method for testing the operation of a DLL-based interface 失效
    用于测试基于DLL的界面的操作的系统和方法

    公开(公告)号：US07289543B2

    公开(公告)日：2007-10-30

    申请号：US10778419

    申请日：2004-02-13

    Applicant: Guangming Yin ,  Bo Zhang

    Inventor： Guangming Yin ,  Bo Zhang

    IPC: H04J3/06

    CPC classification number: H04J3/04 ,  H04J3/0629 ,  H04L1/243 ,  H04L7/0008 ,  H04L25/14

    Abstract: A high-speed bit stream data conversion circuit receives a first bit stream(s) and recovers a clock signal from the first bit stream(s). The data conversion circuit then produces a second bit stream(s) having a second lower bit rate. A control loop adjusts the phase relationship of the recovered clock signal to the first bit stream(s) to minimize data loss when the first bit stream(s) is sliced to produce the second bit stream(s). A reference clock signal produced within a clock circuit is divided to produce a reduced frequency reference clock, which is multiplexed with a test clock signal to produce an output signal. Differentially dividing the output signal produces a series of input signals for an interpolator that selectively weighs and sums the input signals as directed by the control loop to produce the recovered clock signal with the desired phase relationship relative to the first bit stream(s).

    Abstract translation: 高速比特流数据转换电路接收第一比特流并恢复来自第一比特流的时钟信号。 数据转换电路然后产生具有第二较低位速率的第二位流。 当第一比特流被分片以产生第二比特流时，控制环路将恢复的时钟信号的相位关系调整为第一比特流以最小化数据丢失。 在时钟电路内产生的参考时钟信号被分频以产生一个降低的频率参考时钟，该时钟信号与测试时钟信号多路复用以产生一个输出信号。 差分地分割输出信号产生用于内插器的一系列输入信号，其选择性地对控制环路所指示的输入信号进行加权和求和，以产生具有相对于第一位流的所需相位关系的恢复的时钟信号。

    Adaptable voltage control for a variable gain amplifier
    26.
    发明授权
    Adaptable voltage control for a variable gain amplifier 有权
    适用于可变增益放大器的电压控制

    公开(公告)号：US07262659B2

    公开(公告)日：2007-08-28

    申请号：US11559195

    申请日：2006-11-13

    Applicant: Mario Caresosa ,  Guangming Yin

    Inventor： Mario Caresosa ,  Guangming Yin

    IPC: H03F3/45

    CPC classification number: H03F3/4569 ,  H03F3/45197 ,  H03F3/45744 ,  H03F2200/78 ,  H03F2203/45074 ,  H03F2203/45086 ,  H03F2203/45482 ,  H03F2203/45486 ,  H03G1/0088 ,  H03G3/3036 ,  H03G3/3052

    Abstract: A method and apparatus for adaptively controlling a variable gain amplifier (VGA). The operation of the VGA is separated into a low gain mode and a high gain mode and the mode in which the VGA is currently operating in is adaptively sensed. A threshold voltage is compared to a control voltage of the VGA; if the VGA is currently operating in the low gain mode and the control voltage is higher than the threshold voltage, the VGA is switched from the low gain mode to the high gain mode; and if the VGA is currently operating in the high gain mode and the control voltage is lower than the threshold voltage, the VGA is switched from the high gain mode to the low gain mode.

    Abstract translation: 一种用于自适应地控制可变增益放大器（VGA）的方法和装置。 VGA的操作被分为低增益模式和高增益模式，并且自适应地感测VGA当前正在操作的模式。 将门限电压与VGA的控制电压进行比较; 如果VGA当前处于低增益模式并且控制电压高于阈值电压，则VGA从低增益模式切换到高增益模式; 如果VGA当前处于高增益模式并且控制电压低于阈值电压，则VGA从高增益模式切换到低增益模式。

    Current-controlled CMOS circuit using higher voltage supply in low voltage CMOS process
    29.
    发明授权
    Current-controlled CMOS circuit using higher voltage supply in low voltage CMOS process 有权
    电流控制CMOS电路在低电压CMOS工艺中使用更高的电压源

    公开(公告)号：US06911855B2

    公开(公告)日：2005-06-28

    申请号：US10177031

    申请日：2002-06-21

    Applicant: Guangming Yin ,  Ichiro Fujimori ,  Armond Hairapetian

    Inventor： Guangming Yin ,  Ichiro Fujimori ,  Armond Hairapetian

    IPC: H03K3/356 ,  H03K3/3562 ,  H03K17/693 ,  H03K19/094

    CPC classification number: H03K3/356043 ,  H03K3/3562 ,  H03K17/693 ,  H03K19/09432

    Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems. The C3MOS structure enables the use of a power supply voltage that may be larger than the voltage required by the CMOS fabrication process, further enhancing the performance of the circuit.

    Abstract translation: 用于实现超高速电路的各种电路技术使用以常规CMOS工艺技术制造的电流控制CMOS（C 3/4 MOS）逻辑。 包括逆变器/缓冲器，电平移位器，NAND，NOR，异或门，锁存器，触发器等的整个逻辑元件族都使用C 3 MOS技术实现。 通过将高速C“3”MOS逻辑与低功耗常规CMOS逻辑相结合，实现了每个电路应用的功耗和速度之间的最佳平衡。 组合的三极管/ CMOS逻辑允许诸如光纤通信系统中使用的高速收发器之类的电路的更大集成。 C 3 O 3 MOS结构能够使用可能大于CMOS制造工艺所需的电压的电源电压，进一步提高电路的性能。

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