公开(公告)号：US07974337B2

公开(公告)日：2011-07-05

申请号：US12606751

申请日：2009-10-27

Applicant: Afshin Momtaz ,  Mario Caresosa ,  David Kyong-Sik Chung ,  Davide Tonietto ,  Guangming Yin ,  Bruce Currivan ,  Thomas Kolze ,  Ichiro Fujimori

Inventor： Afshin Momtaz ,  Mario Caresosa ,  David Kyong-Sik Chung ,  Davide Tonietto ,  Guangming Yin ,  Bruce Currivan ,  Thomas Kolze ,  Ichiro Fujimori

IPC: H03H7/30

CPC classification number: H04L7/033 ,  H03G3/3084 ,  H03L7/091 ,  H04L25/03057 ,  H04L2025/03375 ,  H04L2025/03617

Abstract: Various example embodiments are disclosed. According to an example embodiment, an apparatus may include a continuous time filter, a decision feedback equalizer, a clock and data recovery circuit, and an adaptation circuit. The adaptation circuit may be configured to adapt equalization according to at least one dithering algorithm by adjusting a delay adjust signal based on a mean square error of equalized data signals.

Abstract translation: 公开了各种示例性实施例。 根据示例实施例，设备可以包括连续时间滤波器，判决反馈均衡器，时钟和数据恢复电路以及适配电路。 适配电路可以被配置为通过基于均衡数据信号的均方误差调整延迟调整信号来根据至少一个抖动算法来适应均衡。

公开(公告)号：US07262659B2

公开(公告)日：2007-08-28

申请号：US11559195

申请日：2006-11-13

Applicant: Mario Caresosa ,  Guangming Yin

Inventor： Mario Caresosa ,  Guangming Yin

IPC: H03F3/45

CPC classification number: H03F3/4569 ,  H03F3/45197 ,  H03F3/45744 ,  H03F2200/78 ,  H03F2203/45074 ,  H03F2203/45086 ,  H03F2203/45482 ,  H03F2203/45486 ,  H03G1/0088 ,  H03G3/3036 ,  H03G3/3052

Abstract: A method and apparatus for adaptively controlling a variable gain amplifier (VGA). The operation of the VGA is separated into a low gain mode and a high gain mode and the mode in which the VGA is currently operating in is adaptively sensed. A threshold voltage is compared to a control voltage of the VGA; if the VGA is currently operating in the low gain mode and the control voltage is higher than the threshold voltage, the VGA is switched from the low gain mode to the high gain mode; and if the VGA is currently operating in the high gain mode and the control voltage is lower than the threshold voltage, the VGA is switched from the high gain mode to the low gain mode.

Abstract translation: 一种用于自适应地控制可变增益放大器（VGA）的方法和装置。 VGA的操作被分为低增益模式和高增益模式，并且自适应地感测VGA当前正在操作的模式。 将门限电压与VGA的控制电压进行比较; 如果VGA当前处于低增益模式并且控制电压高于阈值电压，则VGA从低增益模式切换到高增益模式; 如果VGA当前处于高增益模式并且控制电压低于阈值电压，则VGA从高增益模式切换到低增益模式。

公开(公告)号：US20060028270A1

公开(公告)日：2006-02-09

申请号：US11239927

申请日：2005-09-29

Applicant: Mario Caresosa ,  Guangming Yin

Inventor： Mario Caresosa ,  Guangming Yin

IPC: H03G3/20

CPC classification number: H03F3/4569 ,  H03F3/45197 ,  H03F3/45744 ,  H03F2200/78 ,  H03F2203/45074 ,  H03F2203/45086 ,  H03F2203/45482 ,  H03F2203/45486 ,  H03G1/0088 ,  H03G3/3036 ,  H03G3/3052

Abstract: A method and apparatus for adaptively controlling a variable gain amplifier (VGA). The operation of the VGA is separated into a low gain mode and a high gain mode and the mode in which the VGA is currently operating in is adaptively sensed. A threshold voltage is compared to a control voltage of the VGA; if the VGA is currently operating in the low gain mode and the control voltage is higher than the threshold voltage, the VGA is switched from the low gain mode to the high gain mode; and if the VGA is currently operating in the high gain mode and the control voltage is lower than the threshold voltage, the VGA is switched from the high gain mode to the low gain mode.

公开(公告)号：US20050248396A1

公开(公告)日：2005-11-10

申请号：US10841766

申请日：2004-05-07

Applicant: Mario Caresosa ,  Afshin Momtaz ,  Guangming Yin

Inventor： Mario Caresosa ,  Afshin Momtaz ,  Guangming Yin

IPC: H03F3/45 ,  H03G1/00

CPC classification number: H03G1/007 ,  H03F3/45188 ,  H03F3/45197 ,  H03F2203/45504 ,  H03F2203/45638 ,  H03G1/0029 ,  H03G1/0088

Abstract: An input processing circuit includes a first and second input transistors for receiving a differential pair of first and second input signals, respectively. At least one resistor is coupled between first terminals of the first and second input transistors. The input processing circuit includes a variable gain amplifier (VGA) circuit. At least one first transistor has a gate terminal, and is coupled between the first terminals of the first and second input transistors. At least one second transistor has a gate terminal, and is coupled between the first terminals of the first and second input transistors. A gate switch is coupled to the gate terminal of the at least one second transistor. The at least one first transistor and the at least one second transistor adjust a gain of the input processing circuit in response to a control voltage. The control voltage is applied to the gate terminal of the at least one first transistor, and the control voltage is applied to the gate terminal of the at least one second transistor through the gate switch.

Abstract translation: 输入处理电路包括分别用于接收第一和第二输入信号的差分对的第一和第二输入晶体管。 至少一个电阻耦合在第一和第二输入晶体管的第一端之间。 输入处理电路包括可变增益放大器（VGA）电路。 至少一个第一晶体管具有栅极端子，并且耦合在第一和第二输入晶体管的第一端子之间。 至少一个第二晶体管具有栅极端子，并且耦合在第一和第二输入晶体管的第一端子之间。 栅极开关耦合到至少一个第二晶体管的栅极端子。 所述至少一个第一晶体管和所述至少一个第二晶体管响应于控制电压调整所述输入处理电路的增益。 控制电压被施加到至少一个第一晶体管的栅极端子，并且通过栅极开关将控制电压施加到至少一个第二晶体管的栅极端子。

公开(公告)号：US20100046601A1

公开(公告)日：2010-02-25

申请号：US12606751

申请日：2009-10-27

Applicant: Afshin Momtaz ,  Mario Caresosa ,  David Chung ,  Davide Tonietto ,  Guangming Yin ,  Bruce Currivan ,  Thomas Kolze ,  Ichiro Fujimori

Inventor： Afshin Momtaz ,  Mario Caresosa ,  David Chung ,  Davide Tonietto ,  Guangming Yin ,  Bruce Currivan ,  Thomas Kolze ,  Ichiro Fujimori

IPC: H03K5/159

CPC classification number: H04L7/033 ,  H03G3/3084 ,  H03L7/091 ,  H04L25/03057 ,  H04L2025/03375 ,  H04L2025/03617

Abstract: Various example embodiments are disclosed. According to an example embodiment, an apparatus may include a continuous time filter, a decision feedback equalizer, a clock and data recovery circuit, and an adaptation circuit. The adaptation circuit may be configured to adapt equalization according to at least one dithering algorithm by adjusting a delay adjust signal based on a mean square error of equalized data signals.

Abstract translation: 公开了各种示例性实施例。 根据示例实施例，设备可以包括连续时间滤波器，判决反馈均衡器，时钟和数据恢复电路以及适配电路。 适配电路可以被配置为通过基于均衡数据信号的均方误差调整延迟调整信号来根据至少一个抖动算法来适应均衡。

公开(公告)号：US07623600B2

公开(公告)日：2009-11-24

申请号：US10880959

申请日：2004-06-30

Applicant: Afshin Momtaz ,  Mario Caresosa ,  David Chung ,  Davide Tonietto ,  Guangming Yin ,  Bruce Currivan ,  Thomas Kolze ,  Ichiro Fujimori

Inventor： Afshin Momtaz ,  Mario Caresosa ,  David Chung ,  Davide Tonietto ,  Guangming Yin ,  Bruce Currivan ,  Thomas Kolze ,  Ichiro Fujimori

IPC: H04L27/08

CPC classification number: H04L7/033 ,  H03G3/3084 ,  H03L7/091 ,  H04L25/03057 ,  H04L2025/03375 ,  H04L2025/03617

Abstract: Equalization is provided in a high speed communication receiver that includes in various aspects an automatic gain control input stage, a decision feedback equalizer, a clock and data recovery circuit and equalization control circuits. The automatic gain control stage may include a continuous time filter with an adjustable bandwidth. A threshold adjust signal may be applied to the output of the automatic gain control stage. The equalization control circuits may be implemented in the digital domain and operate at a lower clock speed than the data path.

Abstract translation: 在高速通信接收机中提供均衡，其包括各种方面的自动增益控制输入级，判决反馈均衡器，时钟和数据恢复电路以及均衡控制电路。 自动增益控制级可以包括具有可调节带宽的连续时间滤波器。 阈值调整信号可以应用于自动增益控制级的输出。 均衡控制电路可以在数字域中实现并且以比数据路径更低的时钟速度工作。

公开(公告)号：US20070069817A1

公开(公告)日：2007-03-29

申请号：US11559195

申请日：2006-11-13

Applicant: Mario Caresosa ,  Guangming Yin

Inventor： Mario Caresosa ,  Guangming Yin

IPC: H03G3/10

CPC classification number: H03F3/4569 ,  H03F3/45197 ,  H03F3/45744 ,  H03F2200/78 ,  H03F2203/45074 ,  H03F2203/45086 ,  H03F2203/45482 ,  H03F2203/45486 ,  H03G1/0088 ,  H03G3/3036 ,  H03G3/3052

Abstract: A method and apparatus for adaptively controlling a variable gain amplifier (VGA). The operation of the VGA is separated into a low gain mode and a high gain mode and the mode in which the VGA is currently operating in is adaptively sensed. A threshold voltage is compared to a control voltage of the VGA; if the VGA is currently operating in the low gain mode and the control voltage is higher than the threshold voltage, the VGA is switched from the low gain mode to the high gain mode; and if the VGA is currently operating in the high gain mode and the control voltage is lower than the threshold voltage, the VGA is switched from the high gain mode to the low gain mode.

Abstract translation: 一种用于自适应地控制可变增益放大器（VGA）的方法和装置。 VGA的操作被分为低增益模式和高增益模式，并且自适应地感测VGA当前正在操作的模式。 将门限电压与VGA的控制电压进行比较; 如果VGA当前处于低增益模式并且控制电压高于阈值电压，则VGA从低增益模式切换到高增益模式; 如果VGA当前处于高增益模式并且控制电压低于阈值电压，则VGA从高增益模式切换到低增益模式。

公开(公告)号：US20050271169A1

公开(公告)日：2005-12-08

申请号：US10880959

申请日：2004-06-30

Applicant: Afshin Momtaz ,  Mario Caresosa ,  David Chung ,  Davide Tonietto ,  Guangming Yin ,  Bruce Currivan ,  Thomas Kolze ,  Ichiro Fujimori

Inventor： Afshin Momtaz ,  Mario Caresosa ,  David Chung ,  Davide Tonietto ,  Guangming Yin ,  Bruce Currivan ,  Thomas Kolze ,  Ichiro Fujimori

IPC: H03G3/30 ,  H03L7/091 ,  H04L7/02 ,  H04L7/033 ,  H04L25/03 ,  H04L27/08

CPC classification number: H04L7/033 ,  H03G3/3084 ,  H03L7/091 ,  H04L25/03057 ,  H04L2025/03375 ,  H04L2025/03617

Abstract: Equalization is provided in a high speed communication receiver that includes in various aspects an automatic gain control input stage, a decision feedback equalizer, a clock and data recovery circuit and equalization control circuits. The automatic gain control stage may include a continuous time filter with an adjustable bandwidth. A threshold adjust signal may be applied to the output of the automatic gain control stage. The equalization control circuits may be implemented in the digital domain and operate at a lower clock speed than the data path.

Abstract translation: 在高速通信接收机中提供均衡，其包括各种方面的自动增益控制输入级，判决反馈均衡器，时钟和数据恢复电路以及均衡控制电路。 自动增益控制级可以包括具有可调节带宽的连续时间滤波器。 阈值调整信号可以应用于自动增益控制级的输出。 均衡控制电路可以在数字域中实现并且以比数据路径更低的时钟速度工作。

公开(公告)号：US07135926B2

公开(公告)日：2006-11-14

申请号：US11239927

申请日：2005-09-29

Applicant: Mario Caresosa ,  Guangming Yin

Inventor： Mario Caresosa ,  Guangming Yin

IPC: H03F3/45

CPC classification number: H03F3/4569 ,  H03F3/45197 ,  H03F3/45744 ,  H03F2200/78 ,  H03F2203/45074 ,  H03F2203/45086 ,  H03F2203/45482 ,  H03F2203/45486 ,  H03G1/0088 ,  H03G3/3036 ,  H03G3/3052

Abstract: A method and apparatus for adaptively controlling a variable gain amplifier (VGA). The operation of the VGA is separated into a low gain mode and a high gain mode and the mode in which the VGA is currently operating in is adaptively sensed. A threshold voltage is compared to a control voltage of the VGA; if the VGA is currently operating in the low gain mode and the control voltage is higher than the threshold voltage, the VGA is switched from the low gain mode to the high gain mode; and if the VGA is currently operating in the high gain mode and the control voltage is lower than the threshold voltage, the VGA is switched from the high gain mode to the low gain mode.

Abstract translation: 一种用于自适应地控制可变增益放大器（VGA）的方法和装置。 VGA的操作被分为低增益模式和高增益模式，并且自适应地感测VGA当前正在操作的模式。 将门限电压与VGA的控制电压进行比较; 如果VGA当前处于低增益模式并且控制电压高于阈值电压，则VGA从低增益模式切换到高增益模式; 如果VGA当前处于高增益模式并且控制电压低于阈值电压，则VGA从高增益模式切换到低增益模式。

公开(公告)号：US07034606B2

公开(公告)日：2006-04-25

申请号：US10841766

申请日：2004-05-07

Applicant: Mario Caresosa ,  Afshin Momtaz ,  Guangming Yin

Inventor： Mario Caresosa ,  Afshin Momtaz ,  Guangming Yin

IPC: G06G7/12

CPC classification number: H03G1/007 ,  H03F3/45188 ,  H03F3/45197 ,  H03F2203/45504 ,  H03F2203/45638 ,  H03G1/0029 ,  H03G1/0088

Abstract: An input processing circuit includes a first and second input transistors for receiving a differential pair of first and second input signals, respectively. At least one resistor is coupled between first terminals of the first and second input transistors. The input processing circuit includes a variable gain amplifier (VGA) circuit. At least one first transistor has a gate terminal, and is coupled between the first terminals of the first and second input transistors. At least one second transistor has a gate terminal, and is coupled between the first terminals of the first and second input transistors. A gate switch is coupled to the gate terminal of the at least one second transistor. The at least one first transistor and the at least one second transistor adjust a gain of the input processing circuit in response to a control voltage. The control voltage is applied to the gate terminal of the at least one first transistor, and the control voltage is applied to the gate terminal of the at least one second transistor through the gate switch.

Abstract translation: 输入处理电路包括分别用于接收第一和第二输入信号的差分对的第一和第二输入晶体管。 至少一个电阻耦合在第一和第二输入晶体管的第一端之间。 输入处理电路包括可变增益放大器（VGA）电路。 至少一个第一晶体管具有栅极端子，并且耦合在第一和第二输入晶体管的第一端子之间。 至少一个第二晶体管具有栅极端子，并且耦合在第一和第二输入晶体管的第一端子之间。 栅极开关耦合到至少一个第二晶体管的栅极端子。 所述至少一个第一晶体管和所述至少一个第二晶体管响应于控制电压调整所述输入处理电路的增益。 控制电压被施加到至少一个第一晶体管的栅极端子，并且通过栅极开关将控制电压施加到至少一个第二晶体管的栅极端子。