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    OCN-based moving picture decoder
    22.
    发明授权
    OCN-based moving picture decoder 有权
    基于OCN的运动图像解码器

    公开(公告)号：US08526503B2

    公开(公告)日：2013-09-03

    申请号：US11933060

    申请日：2007-10-31

    Applicant: June-Young Chang ,  Han-Jin Cho

    Inventor： June-Young Chang ,  Han-Jin Cho

    IPC: H04N11/02 ,  H04L12/28

    CPC classification number: H04N19/436 ,  H04N19/42 ,  H04N19/423 ,  H04N19/44

    Abstract: A moving picture decoder further includes a plurality of switches in a mesh configuration, and at least one On-Chip Network (OCN) arranged in a star configuration and coupled to the plurality of switches. The On-Chip Network (OCN) includes a plurality of slave modules coupled to the On-Chip Network (OCN) and arranged in a star configuration.

    Abstract translation: 运动图像解码器还包括网格配置中的多个交换机以及以星形配置并耦合到多个交换机的至少一个片上网络（OCN）。 片上网络（OCN）包括耦合到片上网络（OCN）并以星形配置布置的多个从模块。

    SWITCH BLOCK CIRCUIT IN FIELD PROGRAMMABLE GATE ARRAY
    23.
    发明申请
    SWITCH BLOCK CIRCUIT IN FIELD PROGRAMMABLE GATE ARRAY 有权
    现场可编程门阵列中的开关块电路

    公开(公告)号：US20130147516A1

    公开(公告)日：2013-06-13

    申请号：US13607637

    申请日：2012-09-07

    Applicant: Han Jin CHO ,  Young Hwan Bae

    Inventor： Han Jin CHO ,  Young Hwan Bae

    IPC: H03K19/177

    CPC classification number: H03K19/17744 ,  H03K19/1737 ,  H03K19/1776

    Abstract: A switch block circuit in a field programmable gate array is provided. The switch block circuit includes a configuration memory unit including first group memories and second group memories and a switching unit including first group switching transistors and second group switching transistors. The switch block circuit further includes a selection unit for correspondingly connecting the second group memories with the second group switching transistors depending on an operation mode. The switch block is efficiently reconfigurable depending on the intended use, and configuration memories unused in a specific operation mode may be applied to other purposes.

    Abstract translation: 提供现场可编程门阵列中的开关块电路。 开关块电路包括配置存储单元，其包括第一组存储器和第二组存储器，以及包括第一组开关晶体管和第二组开关晶体管的开关单元。 开关块电路还包括用于根据操作模式相应地将第二组存储器与第二组开关晶体管连接的选择单元。 切换块根据预期用途有效地可重新配置，并且在特定操作模式中未使用的配置存储器可以应用于其他目的。

    CONFIGURATION MEMORY APPARATUS IN FPGA AND ROUTER SYSTEM USING THE SAME
    25.
    发明申请
    CONFIGURATION MEMORY APPARATUS IN FPGA AND ROUTER SYSTEM USING THE SAME 审中-公开
    使用FPGA和路由器系统中的配置存储器设备

    公开(公告)号：US20110149984A1

    公开(公告)日：2011-06-23

    申请号：US12961752

    申请日：2010-12-07

    Applicant: Han Jin CHO ,  Young Hwan Bae

    Inventor： Han Jin CHO ,  Young Hwan Bae

    IPC: H04L12/56 ,  G11C7/10

    CPC classification number: H03K19/177

    Abstract: Disclosed are a configuration memory apparatus and a router system using the same. The configuration memory apparatus includes: a selection unit selecting one of a first external device and a storage unit and receiving data; a register storing input data received from the selection unit; a storage unit storing data received from the register; and an I/O unit controlling transmission and reception of data to and from the register and a second external device.

    Abstract translation: 公开了一种配置存储装置和使用该配置存储装置的路由器系统。 配置存储装置包括：选择单元，选择第一外部设备和存储单元中的一个并接收数据; 存储从所述选择单元接收的输入数据的寄存器; 存储单元，存储从寄存器接收的数据; 以及I / O单元，用于控制向寄存器和从第二外部设备发送和接收数据的I / O单元。

    Slave network interface circuit for improving parallelism of on-chip network and system thereof
    26.
    发明授权
    Slave network interface circuit for improving parallelism of on-chip network and system thereof 有权
    从网络接口电路，用于提高片上网络的并行性及其系统

    公开(公告)号：US07916720B2

    公开(公告)日：2011-03-29

    申请号：US11861360

    申请日：2007-09-26

    Applicant: Jin-Ho Han ,  Han-Jin Cho

    Inventor： Jin-Ho Han ,  Han-Jin Cho

    IPC: H04L12/28

    CPC classification number: G06F15/16

    Abstract: There is provided a slave network interface circuit for improving the parallelism of an On-Chip network, including: a MUX for selecting one of a Write Address inputted from the On-Chip network and a Read Address to read data from a slave module, which is inputted from a slave network interface (SNI) controller, in response to the control of the SNI controller and inputs the selected address to the slave module; and the SNI controller for controlling writing and reading data at the slave module and generating a Read Address to store data read from the slave module and to transfer to the On-Chip network.

    Abstract translation: 提供了一种用于提高片上网络的并行性的从属网络接口电路，包括：用于选择从片上网络输入的写地址中的一个的MUX和从从模块读取数据的读地址， 响应于SNI控制器的控制并将选择的地址输入到从模块，从从网络接口（SNI）控制器输入; 以及用于控制在从模块处的写入和读取数据的SNI控制器，并产生读地址以存储从从模块读取的数据并传送到片上网络。

    SELF-CONTROLLED FUNCTIONAL MODULE, AND CONTROL METHOD THEREFOR AND SYSTEM USING THE SAME
    28.
    发明申请
    SELF-CONTROLLED FUNCTIONAL MODULE, AND CONTROL METHOD THEREFOR AND SYSTEM USING THE SAME 审中-公开
    自控功能模块及其使用的控制方法及系统

    公开(公告)号：US20090013093A1

    公开(公告)日：2009-01-08

    申请号：US12111522

    申请日：2008-04-29

    Applicant: Wonjong KIM ,  Seung-Chul Kim ,  Han-Jin Cho

    Inventor： Wonjong KIM ,  Seung-Chul Kim ,  Han-Jin Cho

    IPC: G06F3/00

    CPC classification number: G06F9/3867

    Abstract: Provided are a self-controlled functional module, and a control method therefor and a system using the same. The functional module, includes: a data input unit for receiving data; a function process unit for performing a specific function based on input data transmitted through the data input unit; a data output unit for outputting a result processed by the function process unit; and an operation control unit for receiving state information individually from the data input unit and the data output unit and controlling operation start of the function process unit based on state information of the data input unit and the data output unit.

    Abstract translation: 提供了一种自我控制的功能模块及其控制方法和使用该功能模块的系统。 功能模块包括：用于接收数据的数据输入单元; 功能处理单元，用于基于通过数据输入单元发送的输入数据执行特定功能; 数据输出单元，用于输出由功能处理单元处理的结果; 以及操作控制单元，用于基于数据输入单元和数据输出单元的状态信息，从数据输入单元和数据输出单元接收状态信息，并且控制功能处理单元的操作开始。

    Crossbar switch architecture for multi-processor SoC platform
    29.
    发明申请
    Crossbar switch architecture for multi-processor SoC platform 有权
    交叉开关架构为多处理器SoC平台

    公开(公告)号：US20070126474A1

    公开(公告)日：2007-06-07

    申请号：US11607515

    申请日：2006-12-01

    Applicant: June Young Chang ,  Han Jin Cho

    Inventor： June Young Chang ,  Han Jin Cho

    IPC: H03K19/173

    CPC classification number: H04L49/101 ,  H04L49/15 ,  H04L49/45

    Abstract: Provided is a crossbar switch architecture appropriate to a multi-processor system-on-a-chip (SoC) platform including a plurality of masters and slaves, capable of high-speed data transfer, allowing the number of masters or slaves therein to be easily increased, and having a simple control structure. The crossbar switch architecture includes 2×1 multiplexers connected in a matrix form consisting of rows and columns. The 2×1 multiplexers each have one input line connected with an output line of a multiplexer at a front column of the same row, and the other input line connected with an input/output line of a column including the corresponding multiplexer, and an output line of a multiplexer at the last column of each row is connected with an input/output line of the row.

    Abstract translation: 提供了一种适用于多处理器片上系统（SoC）平台的交叉开关架构，其包括能够进行高速数据传输的多个主机和从机，从而允许其中的主机或从机的数量容易 增加并具有简单的控制结构。 交叉开关架构包括以行和列组成的矩阵形式连接的2x1多路复用器。 2×1复用器各自具有一个输入线，与同一行前列的多路复用器的输出线连接，另一条输入线与包括相应多路复用器的列的输入/输出线连接，另一条输入线与 每行最后一列的多路复用器与该行的输入/输出线连接。

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