公开(公告)号：US08426305B2

公开(公告)日：2013-04-23

申请号：US13069005

申请日：2011-03-22

Applicant: Hasan Nejad ,  James E. Green

Inventor： Hasan Nejad ,  James E. Green

IPC: H01L21/00

CPC classification number: H01L21/76838 ,  H01L21/76805 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention includes methods of fabricating integrated circuitry. In one implementation, at least two different elevation conductive metal lines are formed relative to a substrate. Then, interconnecting vias are formed in a common masking step between, a) respective of the at least two different elevation conductive metal lines, and b) respective conductive nodes. Interconnecting conductive metal is provided within the interconnecting vias. Other aspects and implementations are contemplated.

Abstract translation: 本发明包括制造集成电路的方法。 在一个实施方案中，相对于基底形成至少两个不同的高度导电金属线。 然后，互连通孔形成在a）相应的至少两个不同高度的导电金属线之间的公共掩模步骤中，以及b）相应的导电节点。 在互连通孔内提供互连导电金属。 考虑了其他方面和实现。

公开(公告)号：US07989251B2

公开(公告)日：2011-08-02

申请号：US11798459

申请日：2007-05-14

Applicant: Hasan Nejad

Inventor： Hasan Nejad

IPC: H01L21/00

CPC classification number: H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/16

Abstract: A variable resistance memory element and method of forming the same. The memory element includes a substrate supporting a bottom electrode having a small bottom contact area. A variable resistance material is formed over the bottom electrodes such that the variable resistance material has a surface that is in electrical communication with the bottom electrode and a top electrode is formed over the variable resistance material. The small bottom electrode contact area reduces the reset current requirement which in turn reduces the write transistor size for each bit.

Abstract translation: 一种可变电阻记忆元件及其形成方法。 存储元件包括支撑具有小的底部接触区域的底部电极的衬底。 在底部电极上形成可变电阻材料，使得可变电阻材料具有与底部电极电连通的表面，并且顶部电极形成在可变电阻材料上。 小的底部电极接触面积减小了复位电流要求，进而降低了每个位的写入晶体管尺寸。

公开(公告)号：US20110171825A1

公开(公告)日：2011-07-14

申请号：US13069005

申请日：2011-03-22

Applicant: Hasan Nejad ,  James E. Green

Inventor： Hasan Nejad ,  James E. Green

IPC: H01L21/768

CPC classification number: H01L21/76838 ,  H01L21/76805 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention includes methods of fabricating integrated circuitry. In one implementation, at least two different elevation conductive metal lines are formed relative to a substrate. Then, interconnecting vias are formed in a common masking step between, a) respective of the at least two different elevation conductive metal lines, and b) respective conductive nodes. Interconnecting conductive metal is provided within the interconnecting vias. Other aspects and implementations are contemplated.

Abstract translation: 本发明包括制造集成电路的方法。 在一个实施方案中，相对于基底形成至少两个不同的高度导电金属线。 然后，互连通孔形成在a）相应的至少两个不同高度的导电金属线之间的公共掩模步骤中，以及b）相应的导电节点。 在互连通孔内提供互连导电金属。 考虑了其他方面和实现。

公开(公告)号：US20080227289A1

公开(公告)日：2008-09-18

申请号：US12121258

申请日：2008-05-15

Applicant: Hasan Nejad ,  James E. Green

Inventor： Hasan Nejad ,  James E. Green

IPC: H01L21/4763

CPC classification number: H01L21/76838 ,  H01L21/76805 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention includes methods of fabricating integrated circuitry. In one implementation, at least two different elevation conductive metal lines are formed relative to a substrate. Then, interconnecting vias are formed in a common masking step between, a) respective of the at least two different elevation conductive metal lines, and b) respective conductive nodes. Interconnecting conductive metal is provided within the interconnecting vias. Other aspects and implementations are contemplated.

Abstract translation: 本发明包括制造集成电路的方法。 在一个实施方案中，相对于基底形成至少两个不同的高度导电金属线。 然后，互连通孔形成在a）相应的至少两个不同高度的导电金属线之间的公共掩模步骤中，以及b）相应的导电节点。 在互连通孔内提供互连导电金属。 考虑了其他方面和实现。

公开(公告)号：US07279762B2

公开(公告)日：2007-10-09

申请号：US11295177

申请日：2005-12-05

Applicant: Hasan Nejad ,  James G. Deak

Inventor： Hasan Nejad ,  James G. Deak

IPC: H01L29/82

CPC classification number: H01L27/222

Abstract: The invention includes a construction comprising an MRAM device between a pair of conductive lines. Each of the conductive lines can generate a magnetic field encompassing at least a portion of the MRAM device. Each of the conductive lines is surrounded on three sides by magnetic material to concentrate the magnetic fields generated by the conductive lines at the MRAM device. The invention also includes a method of forming an assembly containing MRAM devices. A plurality of MRAM devices are formed over a substrate. An electrically conductive material is formed over the MRAM devices, and patterned into a plurality of lines. The lines are in a one-to-one correspondence with the MRAM devices and are spaced from one another. After the conductive material is patterned into lines, a magnetic material is formed to extend over the lines and within spaces between the lines.

Abstract translation: 本发明包括在一对导线之间包括MRAM器件的结构。 每个导线可以产生包围MRAM装置的至少一部分的磁场。 每个导线在三面被磁性材料包围以将由导线产生的磁场集中在MRAM器件上。 本发明还包括形成包含MRAM器件的组件的方法。 在衬底上形成多个MRAM器件。 导电材料形成在MRAM器件上，并被图案化成多条线。 这些线与MRAM器件一一对应，并且彼此间隔开。 在将导电材料图案化成线之后，形成磁性材料以在线之间和线之间的空间内延伸。

公开(公告)号：US20070049015A1

公开(公告)日：2007-03-01

申请号：US11219303

申请日：2005-09-01

Applicant: Hasan Nejad ,  Thomas Figura ,  Gordon Haller ,  Ravi Iyer ,  John Meldrim ,  Justin Harnish

Inventor： Hasan Nejad ,  Thomas Figura ,  Gordon Haller ,  Ravi Iyer ,  John Meldrim ,  Justin Harnish

IPC: H01L21/4763

CPC classification number: H01L21/823835 ,  H01L21/28097 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823814 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10897 ,  H01L29/4975 ,  H01L29/66621 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the silicon in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals diffuses less readily in silicon than silicon does in the metal. An exemplary mixture includes 80% nickel and 20% cobalt. The silicon within the trench is allowed to fully silicide without void formation, despite a relatively high aspect ratio for the trench. Among other devices, recessed access devices (RADs) can be formed by the method for memory arrays.

Abstract translation: 为嵌入硅完全硅化提供了方法和结构。 在沟槽内提供硅。 在硅上提供了一种金属混合物，其中一种金属在硅中比硅中更容易扩散到金属中，而另一种金属在硅中比在金属中的硅更容易扩散。 示例性的混合物包括80％的镍和20％的钴。 尽管沟槽的纵横比相对较高，但沟槽内的硅可以完全无硅化物形成。 在其他设备中，可以通过用于存储器阵列的方法形成凹陷接入设备（RAD）。

公开(公告)号：US20060076635A1

公开(公告)日：2006-04-13

申请号：US11295177

申请日：2005-12-05

Applicant: Hasan Nejad ,  James Deak

Inventor： Hasan Nejad ,  James Deak

IPC: H01L43/00

CPC classification number: H01L27/222

Abstract: The invention includes a construction comprising an MRAM device between a pair of conductive lines. Each of the conductive lines can generate a magnetic field encompassing at least a portion of the MRAM device. Each of the conductive lines is surrounded on three sides by magnetic material to concentrate the magnetic fields generated by the conductive lines at the MRAM device. The invention also includes a method of forming an assembly containing MRAM devices. A plurality of MRAM devices are formed over a substrate. An electrically conductive material is formed over the MRAM devices, and patterned into a plurality of lines. The lines are in a one-to-one correspondence with the MRAM devices and are spaced from one another. After the conductive material is patterned into lines, a magnetic material is formed to extend over the lines and within spaces between the lines.

Abstract translation: 本发明包括在一对导线之间包括MRAM器件的结构。 每个导线可以产生包围MRAM装置的至少一部分的磁场。 每个导线在三面被磁性材料包围以将由导线产生的磁场集中在MRAM器件上。 本发明还包括形成包含MRAM器件的组件的方法。 在衬底上形成多个MRAM器件。 导电材料形成在MRAM器件上，并被图案化成多条线。 这些线与MRAM器件一一对应，并且彼此间隔开。 在将导电材料图案化成线之后，形成磁性材料以在线之间和线之间的空间内延伸。

公开(公告)号：US20050226041A1

公开(公告)日：2005-10-13

申请号：US11150349

申请日：2005-06-13

Applicant: Hasan Nejad ,  Mirmajid Seyyedy

Inventor： Hasan Nejad ,  Mirmajid Seyyedy

IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/22 ,  H01L27/24 ,  G11C11/00

CPC classification number: H01L27/228 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/16 ,  G11C13/004 ,  G11C2013/0054 ,  H01L27/2481

Abstract: This invention relates to memory technology and new variations on memory array architecture to incorporate certain advantages from both cross-point and 1T-1Cell architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1Cell architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple memory cells, which can be stacked vertically above one another in a plurality of memory array layers arranged in a “Z” axis direction.

Abstract translation: 本发明涉及存储器技术以及存储器阵列结构的新变化，以便从交叉点和1T-1Cell架构中融入某些优点。 通过组合这些布局的某些特性，可以利用1T-1Cell架构的快速读取时间和更高的信噪比以及交叉点架构的更高的打包密度。 单个访问晶体管16用于读取可以以“Z”轴方向布置的多个存储器阵列层中的彼此垂直堆叠的多个存储单元。

公开(公告)号：US20050226037A1

公开(公告)日：2005-10-13

申请号：US11142447

申请日：2005-06-02

Applicant: Hasan Nejad ,  Mirmajid Seyyedy

Inventor： Hasan Nejad ,  Mirmajid Seyyedy

IPC: G11C11/00 ,  G11C11/16

CPC classification number: H01L27/228 ,  G11C5/02 ,  G11C11/16

Abstract: This invention relates to an MRAM array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of MRAM cells each column being provided in a respective stacked memory layer.

Abstract translation: 本发明涉及一种在读取操作期间结合来自交叉点和1T-1MTJ架构的某些优点的MRAM阵列体系结构。 通过使用单个访问晶体管来控制1T-1MTJ架构的快速读取时间和更高的信噪比以及交叉点架构的更高的封装密度，以控制每个列的多个堆叠列的MRAM单元的读数 设置在相应的堆叠存储层中。

公开(公告)号：US06940748B2

公开(公告)日：2005-09-06

申请号：US10146113

申请日：2002-05-16

Applicant: Hasan Nejad ,  Mirmajid Seyyedy

Inventor： Hasan Nejad ,  Mirmajid Seyyedy

IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/22 ,  G11C11/14

CPC classification number: G11C11/16 ,  B82Y10/00 ,  G11C11/15 ,  H01L27/228

Abstract: This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple MRAM cells, which can be stacked vertically above one another a plurality of MRAM array layers arranged in a “Z” axis direction.

Abstract translation: 本发明涉及MRAM技术和MRAM阵列体系结构的新变型，其中包含了来自交叉点和1T-1MTJ架构的某些优点。 通过组合这些布局的某些特性，可以利用1T-1MTJ架构的快速读取时间和更高的信噪比以及交叉点架构的更高的封装密度。 单个访问晶体管16用于读取可以以“Z”轴方向布置的多个MRAM阵列层彼此垂直堆叠的多个MRAM单元。