公开(公告)号：US06070201A

公开(公告)日：2000-05-30

申请号：US937798

申请日：1997-09-25

申请人： Yutaka Tanaka ,  Keiji Okamoto ,  Hideo Ishida

发明人： Yutaka Tanaka ,  Keiji Okamoto ,  Hideo Ishida

IPC分类号： G06F3/06 ,  G06F13/368

CPC分类号： G06F3/0626 ,  G06F3/0656 ,  G06F3/0689

摘要： A memory control device having a plurality of data transfer paths including a storage device group comprising a plurality of storage devices for storing data and a buffer memory group comprising multiple buffer memories for storing transferred data, dividing files into multiple blocks for storing blocks in multiple storage devices on different data transfer paths, and executing control to read data from the storage device to be output with a request from a connected terminal to the buffer memory wherein storage devices on different paths create multiple virtual storage device groups, and buffer memories create virtual buffer memory groups. The memory control device comprises a data output control for executing control in a first cycle, the data being temporarily dividedly stored in a prescribed virtual storage device group. In a second cycle the device outputs data stored in the virtual buffer memory group and by alternately repeating first and second cycles, data read from the plural virtual buffer memories group is switched.

摘要翻译： 一种具有多个数据传输路径的存储器控​​制装置，包括包括用于存储数据的多个存储装置的存储装置组和包括用于存储传送数据的多个缓冲存储器的缓冲存储器组，将文件划分成用于存储多个存储块的多个块 设备在不同的数据传输路径上，并且执行控制以从存储设备读取数据，以便从连接的终端到缓冲存储器的请求输出，其中不同路径上的存储设备创建多个虚拟存储设备组，并且缓冲存储器创建虚拟缓冲器 记忆组。 存储器控制装置包括用于在第一周期中执行控制的数据输出控制，数据被暂时地分割存储在规定的虚拟存储装置组中。 在第二周期中，设备输出存储在虚拟缓冲存储器组中的数据，并且通过交替重复第一和第二周期，切换从多个虚拟缓冲存储器组读取的数据。

公开(公告)号：US5664323A

公开(公告)日：1997-09-09

申请号：US560371

申请日：1995-11-17

申请人： Yoshiki Ishida ,  Keiichi Samekawa ,  Kenichi Katayama ,  Yoshifumi Matsumoto ,  Hideo Ishida ,  Koichi Kimura

发明人： Yoshiki Ishida ,  Keiichi Samekawa ,  Kenichi Katayama ,  Yoshifumi Matsumoto ,  Hideo Ishida ,  Koichi Kimura

IPC分类号： B23P21/00 ,  B62D65/00 ,  B62D65/18 ,  B23P19/00

CPC分类号： B62D65/00 ,  Y10T29/49829 ,  Y10T29/49885 ,  Y10T29/53539

摘要： Producing vehicles by using a plurality of production lines allowing the vehicles to successively pass through a welding step, a coating step and an assembling step in each line, in accordance with an increase or decrease in the number of vehicles to be produced in the respective production lines, some of the vehicles in one of the production lines which has less of a margin for production are transferred, after passing through the welding step, to another production line at a portion between its welding step and coating step which line has more of a margin for production. With this arrangement, when it becomes necessary to increase or decrease the number of vehicles in the lines, it is possible to produce vehicles without changing the production ability in the respective steps after the welding step, only by adjusting the number of vehicles in the welding step of the production line which has a less of a margin for production.

摘要翻译： 通过使用多条生产线，根据各生产中要生产的车辆的数量的增加或减少，通过使用多个生产线来使车辆能够依次通过焊接步骤，涂覆步骤和每条线路中的组装步骤 在其中一条生产线较少的生产线中的一些生产线中的一些车辆在通过焊接步骤之后，在其焊接步骤和涂覆步骤之间的部分被转移到另一个生产线上，该线具有更多的 生产保证金。 通过这种布置，当需要增加或减少线路中的车辆数量时，只有通过调整焊接中的车辆数量，才能在焊接步骤之后的各个步骤中生产车辆而不改变生产能力 生产线步伐较低，生产利润较低。

公开(公告)号：US5504697A

公开(公告)日：1996-04-02

申请号：US360359

申请日：1994-12-21

申请人： Hideo Ishida

发明人： Hideo Ishida

IPC分类号： G06F7/00 ,  G06F7/02 ,  G06F7/48 ,  G06F7/74 ,  G06F7/38 ,  G06F11/00

CPC分类号： G06F9/30021 ,  G06F7/026 ,  G06F7/48 ,  G06F7/49921

摘要： Disclosed herein is a limiter circuit for limiting an output data to a limit value when an input data exceeds in value the limit value. The limiter circuit includes an encoder responding to the input data and producing a first data indicative of an effective digit number of the value of the input data, a comparator comparing the first data with a second data indicative of an effective digit number of the limit value, and a decoder responding to the second data and producing a third data indicative of the limit value. One of the input data and the third data is selected and outputted as the output data through a selector responding to a comparison output of the comparator.

摘要翻译： 这里公开了一种限制器电路，用于当输入数据超过限制值时将输出数据限制到极限值。 所述限制器电路包括对所述输入数据进行响应的编码器，并且产生指示所述输入数据的值的有效数字编号的第一数据;比较器，将所述第一数据与指示所述极限值的有效数字编号的第二数据进行比较 以及响应于所述第二数据并产生指示所述极限值的第三数据的解码器。 输入数据和第三数据中的一个被选择并通过响应于比较器的比较输出的选择器输出作为输出数据。

公开(公告)号：US5434490A

公开(公告)日：1995-07-18

申请号：US98956

申请日：1993-07-29

申请人： Hideo Ishida ,  Takashi Tanaka ,  Haruhiro Watanabe

发明人： Hideo Ishida ,  Takashi Tanaka ,  Haruhiro Watanabe

IPC分类号： B61L23/00 ,  B62D1/28 ,  G05D1/00 ,  G05D1/02 ,  B65G1/06

CPC分类号： G05D1/0022 ,  B61L23/005 ,  B62D1/28 ,  G05D1/0244 ,  G05D1/0263 ,  G05D1/0282 ,  G05D1/0274 ,  G05D2201/0216

摘要： An article transport system includes a plurality of article loading and unloading stations, at least one carriage for running between the stations to transport articles therebetween, and a base station installed on the ground to provide the carriage with running instructions at an article transport request received from one of the stations. Each of the base station, loading and unloading stations and carriage includes a radio communication unit. Article transport requests and running instructions are transmitted by radio communication.

摘要翻译： 物品输送系统包括多个物品装卸站，至少一个用于在车站之间运行的运输工具之间运送物品的托架以及安装在地面上的基站，以便在运送指令的基础上提供运送指令， 其中一个站。 基站，装卸台和托架均包括无线电通信单元。 通过无线电通信传送文章传输请求和运行指令。

公开(公告)号：US3953069A

公开(公告)日：1976-04-27

申请号：US568202

申请日：1975-04-15

申请人： Takeo Tamura ,  Hideo Ishida

发明人： Takeo Tamura ,  Hideo Ishida

IPC分类号： B60N2/20 ,  B60N2/235 ,  B60N1/02

CPC分类号： B60N2/20 ,  B60N2/2354 ,  Y10S148/136 ,  Y10T16/54024 ,  Y10T16/540254

摘要： A seat back tilts forward when an actuating lever is pulled, and remains forward after the lever is released. The seat back is restored to a desired operating position by pushing it backward until it stops moving. The desired position is set by pulling a release lever, pushing the seat back to the desired position, and releasing the release lever.

摘要翻译： 当执行杆被拉动时，座椅靠背向前倾斜，并且在释放杆后保持向前。 通过向后推动座椅靠背恢复到所需的操作位置，直到其停止移动。 通过拉动释放杆，将座椅推回到所需位置并释放释放杆来设定所需的位置。

公开(公告)号：US07165307B2

公开(公告)日：2007-01-23

申请号：US08627270

申请日：1996-04-04

申请人： Hideaki Tojo ,  Hideo Ishida ,  Hisashi Kurota ,  Takao Arasawa ,  Nobuyuki Okita

发明人： Hideaki Tojo ,  Hideo Ishida ,  Hisashi Kurota ,  Takao Arasawa ,  Nobuyuki Okita

IPC分类号： B23P25/00

CPC分类号： B05D5/00 ,  B05D1/32 ,  B05D1/325 ,  B05D3/0209 ,  B05D3/0254 ,  Y10T29/49812 ,  Y10T29/49885

摘要： There are disclosed a method and apparatus for applying a strippable paint to a large-sized product finished with a sprayed coating, such as an automobile, to form a protective film on the surface of the coating. The product is conventionally kept in stock for a period of time before it is shipped. Contaminations such as dust are washed away from the surface of the product. Then, the strippable paint is applied, preliminarily dried, and non-preliminarily dried to form the protective film out of the strippable paint on the surface of the coating. This protective film is formed easily, appropriately, and reliably. The obtained protective film has a uniform and sufficient thickness. Even if the surface contains unapplied regions to which the paint should not be applied, the paint can be applied to the whole surface of the coating while avoiding the unapplied regions according to the invention. The application can be performed easily and reliably without leaving unapplied portions around the unapplied regions.

摘要翻译： 公开了一种将可剥离涂料施加到用喷涂涂层如汽车完成的大型产品上以在涂层的表面上形成保护膜的方法和装置。 产品通常在发货前保存一段时间。 诸如灰尘的污染物从产品的表面洗掉。 然后，将可剥离涂料进行预干燥，并进行非预先干燥，从涂膜表面的可剥离涂料中形成保护膜。 该保护膜容易，适当且可靠地形成。 所获得的保护膜具有均匀且足够的厚度。 即使表面含有不应用涂料的未涂覆区域，也可以将涂料施加到涂层的整个表面，同时避免根据本发明的未涂覆区域。 可以容易且可靠地执行应用，而不会在未应用的区域周围留下未应用的部分。

公开(公告)号：US6029189A

公开(公告)日：2000-02-22

申请号：US986785

申请日：1997-12-08

申请人： Hideo Ishida ,  Yutaka Tanaka

发明人： Hideo Ishida ,  Yutaka Tanaka

IPC分类号： G06F3/06 ,  H04N7/173 ,  G06F13/00

CPC分类号： G06F3/061 ,  G06F3/0635 ,  G06F3/0689 ,  H04N7/17336

摘要： In a data transfer system in which when a first to fourth terminals require reading data, the data are read out of a first to fourth storages to be stored in a first and second buffer memories while a first and second virtual groups of storages are alternately switched every constant cycle, and thereafter a first and second data sending units send the data stored in the first and second buffer memories to the terminals; on the other hand, when the first to fourth terminals require writing data, received data is divided in a way to distribute the process loads of data read and data write of the divided data equally into a first and second data transfer units. At the same time, the data are stored in the first and second buffer memories of the first and second data transfer units, and thereafter the data are written into the first to fourth storages while switching the first and second virtual groups of storages alternately. As a result, the load of transferring data to the terminals is not concentrated on a particular data transfer unit in the data transfer system, even when the rate of request-to-reads from the terminals changes or differs from those of others.

摘要翻译： 在第一至第四终端需要读取数据的数据传输系统中，从第一至第四存储器中读出数据以存储在第一和第二缓冲存储器中，同时第一和第二虚拟存储组交替地切换 每个恒定周期，然后第一和第二数据发送单元将存储在第一和第二缓冲存储器中的数据发送到终端; 另一方面，当第一至第四终端需要写入数据时，以将分割数据的数据读取和数据写入的处理负载均等地分配到第一和第二数据传送单元的方式分割接收数据。 同时，将数据存储在第一和第二数据传送单元的第一和第二缓冲存储器中，然后数据被写入第一至第四存储器，同时交替地切换第一和第二虚拟存储组。 结果，即使当从终端请求读取的速率变化或与其他的不同时，向终端传送数据的负载也不集中在数据传送系统中的特定数据传送单元上。

公开(公告)号：US5553257A

公开(公告)日：1996-09-03

申请号：US189680

申请日：1994-02-01

申请人： Hideo Ishida ,  Yasushi Ooi

发明人： Hideo Ishida ,  Yasushi Ooi

IPC分类号： H03M7/42 ,  H04N7/26 ,  H04N7/30 ,  G06F12/00

CPC分类号： H03M7/42 ,  H04N19/13 ,  H04N19/60 ,  H04N19/91

摘要： An address generating circuit having a two-dimensional coding table which has respective coded words corresponding to a combination of x and y where the value of event A is determined as x and the value of event B as y (x and y are positive integers) between two events A and B, and stores the coded words in an address corresponding to each combination of x and y; coincidence detectors which input the values x and y of the events A and B and detect whether these values coincide with the integer of 1 to S (S is the maximum number among the integers satisfying S+log.sub.2 S

摘要翻译： 具有二维编码表的地址生成电路，其具有对应于事件A的值被确定为x的事件A的值和事件B的值对应于x和y的组合的各个编码字，y（x和y是正整数） 在两个事件A和B之间，并且将编码的字存储在与x和y的每个组合相对应的地址中; 输入事件A和B的值x和y并检测这些值是否与1到S的整数一致的符合检测器（S是满足S + log2S

公开(公告)号：US5455908A

公开(公告)日：1995-10-03

申请号：US83474

申请日：1993-06-30

申请人： Hideo Ishida

发明人： Hideo Ishida

IPC分类号： G06F12/00 ,  G06F9/345 ,  G06T1/60 ,  G06T9/00 ,  H04N7/26 ,  H04N7/30 ,  H04N7/50 ,  G06F12/06

CPC分类号： G06F9/345 ,  H04N19/433 ,  H04N19/51 ,  H04N19/61 ,  H04N19/98

摘要： In an address formation circuit for an image processing, an address formation is separately processed in parallel like a pipeline by first and second address calculation means. The first address calculation means controllable by a program calculates a head address of a macroblock, and the second address calculation means calculates addresses of pixels within the macroblock on the basis of the head address calculated by the first address calculation means. An instruction memory stores the program and a data memory and a data file memory store address moving amounts required the calculations. A sequence controller controls an exclusive hardware. Hence, a high speed memory access like a real time image processing in the address formation can be possible and, when a complicated address pattern is required, an overhead of the address formation time in the instruction processing can be prevented.

摘要翻译： 在用于图像处理的地址形成电路中，通过第一和第二地址计算装置，像流水线一样并行处理地址形成。 由程序控制的第一地址计算装置计算宏块的头地址，第二地址计算装置基于由第一地址计算装置计算的头地址来计算宏块内的像素的地址。 指令存储器存储程序和数据存储器以及数据文件存储器存储地址移动量所需的计算。 序列控制器控制专用硬件。 因此，像地址形成中的实时图像处理那样的高速存储器访问是可能的，并且当需要复杂的地址模式时，可以防止指令处理中的地址形成时间的开销。

公开(公告)号：US4817750A

公开(公告)日：1989-04-04

申请号：US46871

申请日：1987-05-04

申请人： Hideo Ishida ,  Susumu Moriya ,  Takuo Taya ,  Hiroshi Shimokata

发明人： Hideo Ishida ,  Susumu Moriya ,  Takuo Taya ,  Hiroshi Shimokata

IPC分类号： B65G43/00 ,  G05D1/02 ,  G05D1/03

CPC分类号： G05D1/0263 ,  G05D2201/0216

摘要： A control system for enabling a conveyor cart or carts to run automatically along a running track. The or each cart comprises a sensor for detecting a guiding line extending along the running track and outputting detection data, and a steering control device operable in response to the detection data for steering the conveyor cart to follow the guiding line. The sensor is switchable for selectively detecting right and left edges of the guiding line. The right edge is detected for permitting the cart to run through a junction along a rightwardly curved branching or merging line. The left edge is detected for permitting the cart to run through a junction along a leftwardly curved branching or merging line.

摘要翻译： 一种用于使输送机推车或推车沿着运行的轨道自动运行的控制系统。 该或每个推车包括用于检测沿着行驶轨道延伸的引导线并输出检测数据的传感器，以及可响应于用于转向传送车以跟随引导线的检测数据而操作的转向控制装置。 传感器可切换，用于选择性地检测引导线的左右边缘。 检测右边缘以允许推车沿着右侧弯曲的分支或合并线穿过连接点。 检测左边缘以允许推车沿着左弯曲的分支或合并线穿过连接点。