公开(公告)号：US6154718A

公开(公告)日：2000-11-28

申请号：US41504

申请日：1998-03-12

申请人： Hironori Sakamoto

发明人： Hironori Sakamoto

IPC分类号： H01L21/265 ,  G06F17/50 ,  G06F19/00 ,  G06Q50/00 ,  G06Q50/04 ,  H01L21/00 ,  G06G7/48 ,  G06G7/58

CPC分类号： G06F17/5018 ,  G06F2217/80

摘要： A distribution of the concentration of initial point-defects which generate in an ion implanting process is obtained with an ion implanting simulator. As a local function of the distribution, the distribution of the intensity of absorption of point-defects is obtained. A term of absorption of point-defects obtained from the distribution of the intensity is included in a diffusion equation. With the resultant diffusion equation, the diffusion simulation is performed. Thus the simulation using the diffusion equation may be extended to two or three dimension and cope with various ion implanting conditions.

摘要翻译： 使用离子注入模拟器获得在离子注入过程中产生的初始点缺陷的浓度分布。 作为分布的局部函数，获得点缺陷吸收强度的分布。 从强度分布获得的点缺陷的吸收项包括在扩散方程式中。 通过得到的扩散方程，进行扩散模拟。 因此，使用扩散方程的模拟可以扩展到二维或三维，并应对各种离子注入条件。

公开(公告)号：US5412342A

公开(公告)日：1995-05-02

申请号：US4466

申请日：1993-01-14

申请人： Hironori Sakamoto ,  Akira Ito ,  Toshio Nojima

发明人： Hironori Sakamoto ,  Akira Ito ,  Toshio Nojima

IPC分类号： H03F3/68 ,  H03F1/32 ,  H03F3/60

CPC分类号： H03F1/3229 ,  H03F3/602 ,  H03F2201/3218

摘要： For supply to first and second feedforward distortion compensating circuits 33(1), 33(2) connected in parallel, a two-divider 31 divides into signals of a common phase and a common amplitude an input or composite radio frequency signal supplied to an input terminal 11. The composite radio frequency signal collectively has a plurality of radio frequency signals of different frequencies. A two-combiner 35 combines component outputs of the feedforward circuits in inphase as an amplified output signal which is supplied to an output terminal 13. In general, N feedforward circuits (N being an integer not less than two) are connected in parallel and are supplied with the input radio frequency signal through an N-divider. Component outputs of the feedforward circuits are combined in inphase as the output signal by an N-combiner. Alternatively, the input radio frequency signal is divided into signals of a predetermined phase difference and of a common amplitude by the N-divider. In this case, the component outputs of the feedforward circuits are combined in a phase of cancelling the predetermined phase difference by the N-combiner.

摘要翻译： 为了供应到并联连接的第一和第二前馈失真补偿电路33（1），33（2），二分频器31将提供给输入端的输入或复合射频信号分为公共相位和公共振幅信号 复合射频信号共同具有不同频率的多个射频信号。 双组合器35将前馈电路的分量输出同相作为被提供给输出端子13的放大输出信号。通常，N个前馈电路（N是不小于2的整数）并联连接， 通过N分频器提供输入射频信号。 前馈电路的分量输出由N组合器同相作为输出信号组合。 或者，输入射频信号被N分频器分成预定相位差和公共振幅的信号。 在这种情况下，前馈电路的分量输出以N组合器消除预定相位差的相位组合。

公开(公告)号：US5394120A

公开(公告)日：1995-02-28

申请号：US217878

申请日：1994-03-25

申请人： Hironori Sakamoto ,  Akira Ito ,  Masaaki Fujiwara ,  Toshio Nojima

发明人： Hironori Sakamoto ,  Akira Ito ,  Masaaki Fujiwara ,  Toshio Nojima

IPC分类号： G01R31/28 ,  H03F1/32 ,  G01R19/00

CPC分类号： G01R31/2825 ,  H03F1/3229

摘要： A device for testing an amplifier. A plurality of PN modulators are provided corresponding to a plurality of oscillators at stages preceding or following them, or fluctuation is given to division ratios at the oscillators. Since each of n carriers combined by a combiner contains phase fluctuation, the possibility that the peaks will overlap each other or that the carriers having opposite phases will negate each other is very low. The peak power in signals supplied to the amplifier to be tested is unlikely to vary, enabling accurate evaluation or testing.

摘要翻译： 用于测试放大器的设备。 在它们之前或之后的阶段对应于多个振荡器提供多个PN调制器，或者在振荡器处给出分频比的波动。 由于由组合器组合的n个载波中的每一个包含相位波动，所以峰将彼此重叠或者具有相反相位的载波彼此否定的可能性非常低。 提供给待测放大器的信号的峰值功率不太可能发生变化，从而能够进行准确的评估或测试。

公开(公告)号：US08296700B2

公开(公告)日：2012-10-23

申请号：US12791535

申请日：2010-06-01

申请人： Hironori Sakamoto

发明人： Hironori Sakamoto

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A design supporting apparatus of a semiconductor device, includes sections to perform: setting an impurity concentration with respect to a channel direction and a depth direction to node points arranged discretely in a channel region of a model transistor based on a predetermined concentration distribution rule; calculating an electric characteristic of the model transistor by using the impurity concentration; and storing the impurity concentration as a model parameter of the model transistor in a storage unit, when the calculated electric characteristic and an electric characteristic prepared previously are coincident with each other within a predetermined range. The device characteristic calculating section calculates a surface potential to each of the node points by reducing a dimension of the impurity concentration in the depth direction, corrects the surface potential based on interaction between the node points adjacent to each other, and calculates the electric characteristic by using the corrected surface potential.

摘要翻译： 一种半导体器件的设计支持装置，包括：基于预定浓度分布规则，将相对于沟道方向和深度方向的杂质浓度设置为离散地设置在模型晶体管的沟道区域中的节点; 通过使用杂质浓度计算模型晶体管的电特性; 以及当预先计算的电特性和电特性在预定范围内彼此一致时，将杂质浓度作为模型晶体管的模型参数存储在存储单元中。 器件特性计算部分通过减小深度方向上的杂质浓度的尺寸来计算每个节点的表面电位，根据彼此相邻的节点之间的相互作用来校正表面电位，并且通过 使用校正后的表面电位。

公开(公告)号：US08250508B2

公开(公告)日：2012-08-21

申请号：US12482016

申请日：2009-06-10

申请人： Hironori Sakamoto

发明人： Hironori Sakamoto

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5018

摘要： An analysis and design apparatus for semiconductor device, which utilizes a transistor model using accurate channel impurity concentration distribution are provided. The analysis and design apparatus includes a parameter setting portion that divides a channel region into a plurality of regions, and temporarily sets a plurality of impurity concentrations for the plurality of regions as a plurality of parameters. Further, the analysis and design apparatus includes an element characteristic calculation portion that values of electric characteristics of the transistor using surface potential that is calculated by solving a Poisson equation using a plurality of effective impurity concentrations. Moreover, the determination portion compares the calculated values with measured values read from a storage portion based on the structure information, and determines that the plurality of parameters for the transistor when the measured values correspond to the calculated values.

摘要翻译： 提供一种使用精确的通道杂质浓度分布的晶体管模型的半导体器件的分析和设计装置。 分析设计装置包括将通道区域划分成多个区域的参数设定部，并且将多个区域的多个杂质浓度临时设定为多个参数。 此外，分析和设计装置包括元件特性计算部分，其使用通过使用多个有效杂质浓度求解泊松方程计算的表面电位的晶体管的电特性值。 此外，确定部分基于结构信息将计算值与从存储部分读取的测量值进行比较，并且当测量值对应于计算值时，确定晶体管的多个参数。

公开(公告)号：US20090115526A1

公开(公告)日：2009-05-07

申请号：US11994702

申请日：2005-07-05

申请人： Tamaki Honda ,  Hironori Sakamoto ,  Kenjiro Okadome

发明人： Tamaki Honda ,  Hironori Sakamoto ,  Kenjiro Okadome

IPC分类号： H03F3/16 ,  H03G3/20

CPC分类号： H03F1/301 ,  H03F3/193 ,  H03F2200/108 ,  H03F2200/18 ,  H03F2200/453

摘要： A FET bias circuit applies a bias voltage that is not adjusted separately to an amplifying element FET of a FET amplifying circuit. In the FET bias circuit is provided a monitor element FET m having a gate connected to the gate of the amplifying element FET a and a source connected to the source of the amplifying element FET a, respectively, and having a drain current with respect to the bias voltage substantially proportional to the drain current of the amplifying element FET a. In the FET bias circuit is further provided a fixed bias circuit for applying the bias voltage so that the amplifying element FET a enters a predetermined operating class by applying a bias voltage to the monitor element FET m so that a drain current flowing to the monitor element FET m enters a predetermined operating class.

摘要翻译： FET偏置电路施加不与FET放大电路的放大元件FET单独调整的偏置电压。 在FET偏置电路中，提供了具有连接到放大元件FETa的栅极的栅极和连接到放大元件FET a的源极的源极的监视元件FET m，并且具有相对于 基本上与放大元件FET a的漏极电流成比例的偏置电压。 在FET偏置电路中还设置有用于施加偏置电压的固定偏置电路，使得放大元件FETa通过向监视元件FET m施加偏置电压而进入预定的工作等级，使得流向监视元件的漏极电流 FET m进入预定的操作类。

公开(公告)号：US20070233447A1

公开(公告)日：2007-10-04

申请号：US11730012

申请日：2007-03-29

申请人： Ryo Miyata ,  Hironori Sakamoto

发明人： Ryo Miyata ,  Hironori Sakamoto

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A circuit simulation method for estimating electrical characteristics of a semiconductor device is provided. The circuit simulation method includes: (A) generating a device model parameter of a semiconductor device model used in a circuit simulation; and (B) executing the circuit simulation by using the semiconductor device model and the generated device model parameter. The (A) step includes: (a) generating a plurality of device model parameters with respect to a plurality of different temperatures; and (b) generating the device model parameter corresponding to a specified temperature by interpolating between the plurality of device model parameters.

摘要翻译： 提供了一种用于估计半导体器件的电特性的电路仿真方法。 电路仿真方法包括：（A）生成电路仿真中使用的半导体器件模型的器件模型参数; 和（B）使用半导体器件模型和生成的器件模型参数执行电路仿真。 （A）步骤包括：（a）产生关于多个不同温度的多个装置模型参数; 以及（b）通过在所述多个设备模型参数之间进行插值来生成对应于指定温度的设备模型参数。

公开(公告)号：US6148276A

公开(公告)日：2000-11-14

申请号：US154986

申请日：1998-09-17

申请人： Hironori Sakamoto

发明人： Hironori Sakamoto

IPC分类号： H01L21/22 ,  G06F17/50 ,  G06F19/00 ,  H01L21/00

CPC分类号： G06F17/5018

摘要： A diffusion simulating method which is capable of defining an impurity flux even if one impurity in one material region is changed into plural types of impurities in the other material region on a material interface. For simulating the diffusion of the impurities in a system which includes a first material region, a second material region and a interface disposed between the first material region and the second material region, impurity flux J(i.sub.A,j.sub.B) on the A/B interface is defined between optional impurity i.sub.A in material region A and optional impurity j.sub.B in material region B. Then, total fluxes J.sup.total (i.sub.A), J.sup.total (j.sub.B) of each type of impurity are determined and added to impurity diffusion equations, and simultaneous equations are set up by these diffusion equations and solved.

摘要翻译： 即使在一个材料区域中的一个杂质在材料界面上的另一个材料区域中变成多种类型的杂质，也能够定义杂质磁通量的扩散模拟方法。 为了模拟包括第一材料区域，第二材料区域和布置在第一材料区域和第二材料区域之间的界面的系统中的杂质的扩散，A / B界面上的杂质通量J（iA，jB） 在材料区域A中的可选杂质iA和材料区域B中的任选杂质jB之间定义。然后确定每种类型杂质的总通量Jtotal（iA），Jtotal（jB），并将其加到杂质扩散方程中，联立方程式 通过这些扩散方程建立并解决。