公开(公告)号：US20080074929A1

公开(公告)日：2008-03-27

申请号：US11838605

申请日：2007-08-14

Applicant: Hitoshi SHIGA ,  Kiyofumi Sakurai ,  Kenji Mima

Inventor： Hitoshi SHIGA ,  Kiyofumi Sakurai ,  Kenji Mima

IPC: G11C11/34 ,  G06F17/50 ,  H01L23/52

CPC classification number: G06F17/5077 ,  G11C5/025 ,  H01L27/0207 ,  H01L27/11898

Abstract: An ASIC includes a first-wire extended in a first-direction and a second-wire extended in a parallel direction to the first-wire and both are placed on a first-wire layer; and a third-wire placed on a second-wire layer above the first-wire layer and is extended above the wire and above the second-wire in a second-direction which intersects the first-direction and passing through a first via-hole is connected to the first-wire, and a fourth-wire separated from the third-wire extended in a parallel direction above the first-wire and above the second-wire and a fifth-wire separated from both the third-wire and the fourth-wire and extended in a parallel direction in a smallest space and passing through a second via-hole is connected to the second-wire, wherein, one end of the fifth-wire is extended to the center between the second-wire and the first-wire from above the second-wire.

Abstract translation: ASIC包括沿第一方向延伸的第一线和与第一线并联延伸的第二线，并且两者均放置在第一线层上; 以及放置在所述第一线层上方的二线层上并且在所述线的上方延伸并且在与所述第一方向相交并穿过第一通孔的第二方向上方的所述第二线上的第三线是 连接到第一线，以及与第三线分离的第四线，该第三线在第一线上方平行并且在第二线上方延伸，以及与第三线和第四线分离的第五线， 并且在最小的空间中沿平行方向延伸并穿过第二通孔的第二线连接到第二线，其中，第五线的一端延伸到第二线和第一线之间的中心， 电线从二线以上。

公开(公告)号：US20070097750A1

公开(公告)日：2007-05-03

申请号：US11564887

申请日：2006-11-30

Applicant: Hitoshi SHIGA ,  Chih-Hung Wang ,  Chin Lin

Inventor： Hitoshi SHIGA ,  Chih-Hung Wang ,  Chin Lin

IPC: G11C11/34

CPC classification number: G11C16/344 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/16 ,  G11C2211/5621

Abstract: A semiconductor memory device includes a memory cell array, data buffer, and column switch. The data buffer senses the potential of a bit line to determine data in a selected memory cell and hold readout data in a read. The data buffer detects both whether the whole data buffer holds “0” data and whether the whole data buffer holds “1” data. The column switch selects part of the data buffer and connects the part to a bus.

Abstract translation: 半导体存储器件包括存储单元阵列，数据缓冲器和列开关。 数据缓冲器检测位线的电位以确定所选择的存储单元中的数据并保持读取中的读出数据。 数据缓冲器检测整个数据缓冲器是否保持“0”数据以及整个数据缓冲器是否保持“1”数据。 列开关选择数据缓冲区的一部分，并将部件连接到总线。

公开(公告)号：US07161835B2

公开(公告)日：2007-01-09

申请号：US10957826

申请日：2004-10-05

Applicant: Hitoshi Shiga

Inventor： Hitoshi Shiga

IPC: G11C16/06

CPC classification number: G11C16/344 ,  G11C16/0483

Abstract: A semiconductor memory device including: a cell array with electrically rewritable and non-volatile memory cells arranged therein; a sense amplifier circuit configured to read data of and write data into the cell array; and a controller configured to control read, write and erase of the cell array, wherein the controller executes an erase sequence for erasing a selected block in the cell array in response to erase command and address input in such a way of: executing a first erase-verify operation for verifying an erase state of the selected block; ending the erase sequence if the erase state of the selected block has been verified by the first erase-verify operation; whereas executing an erase operation for the selected block if the erase state has not been verified.

Abstract translation: 一种半导体存储器件，包括：具有布置在其中的电可重写和非易失性存储单元的单元阵列; 读出放大器电路，被配置为读取数据并将数据写入单元阵列; 以及控制器，其被配置为控制所述单元阵列的读取，写入和擦除，其中所述控制器响应于擦除命令和地址输入执行用于擦除所述单元阵列中的所选块的擦除序列，其方式为：执行第一擦除 - 验证所选块的擦除状态的操作; 如果所选块的擦除状态已被第一次擦除验证操作验证，则结束擦除序列; 而如果擦除状态尚未被验证，则对所选择的块执行擦除操作。

公开(公告)号：US20060203596A1

公开(公告)日：2006-09-14

申请号：US11193462

申请日：2005-08-01

Applicant: Hitoshi Shiga

Inventor： Hitoshi Shiga

IPC: G11C8/00

CPC classification number: G11C8/12 ,  G11C16/0483 ,  G11C16/08

Abstract: A semiconductor integrated circuit device comprises several blocks including a word line connected with a memory cell, a row decoder selecting the word line, and a block decoder selecting the block. The block decoder includes a logical address register holding logical block address corresponding to the several blocks and a block status register holding a block status. The block decoder selects a block in which input block address and input block status match with held logical block address and held block status, respectively.

Abstract translation: 半导体集成电路器件包括若干块，包括与存储单元连接的字线，选择字线的行解码器和选择该块的块解码器。 块解码器包括保存对应于几个块的逻辑块地址的逻辑地址寄存器和保持块状态的块状态寄存器。 块解码器分别选择输入块地址和输入块状态与保持的逻辑块地址匹配并保持块状态的块。

公开(公告)号：US20060050314A1

公开(公告)日：2006-03-09

申请号：US11216215

申请日：2005-09-01

Applicant: Hitoshi Shiga ,  Chih-Chung Chen ,  Chih-Hung Wang ,  Sheng-Lin Hung

Inventor： Hitoshi Shiga ,  Chih-Chung Chen ,  Chih-Hung Wang ,  Sheng-Lin Hung

IPC: G06K15/00

CPC classification number: G11C16/102 ,  G11C16/0483 ,  G11C16/26 ,  G11C2207/2236 ,  G11C2216/14

Abstract: A memory system includes a memory cell array, a bit line switch, first and second page buffers, a column switch, an error correction circuit, and control circuits. The second page buffer can swap data with the first page buffer. The control circuits controls the bit line switch and the first and second page buffers, sequentially reads, page by page, one or more pages from the mth (m is a positive integer) page to the nth (n is an integer greater than m) page of the first block in the memory cell array, controls the error correction circuit to perform error correction calculation by the error correction circuit, controls the first and second data buffers and the bit line switch, and controls to perform write in the second block in the erase state in the memory cell array.

Abstract translation: 存储器系统包括存储单元阵列，位线开关，第一和第二页缓冲器，列开关，纠错电路和控制电路。 第二页缓冲区可以与第一页缓冲区交换数据。 控制电路控制位线开关，第一和第二页缓冲器逐页依次读取从第m（m为正整数）页到第n（n为大于m的整数）的一页或多页， 控制误差校正电路进行误差校正电路的误差校正计算，控制第一和第二数据缓冲器和位线开关，并控制在第二块中执行写入 存储单元阵列中的擦除状态。

公开(公告)号：US06982904B2

公开(公告)日：2006-01-03

申请号：US10856851

申请日：2004-06-01

Applicant: Hitoshi Shiga

Inventor： Hitoshi Shiga

IPC: G11C16/06

CPC classification number: G11C16/26 ,  G06F11/1068 ,  G11C16/0483 ,  G11C16/3418

Abstract: A non-volatile semiconductor memory device includes: a cell array having electrically rewritable and non-volatile memory cells arranged therein; and a sense amplifier circuit configured to detect voltage change of a bit line in the cell array, thereby reading data of a selected memory cell coupled to the bit line, wherein the sense amplifier circuit is controlled to read data at plural timings within a period in which the bit line voltage is changing in correspondence with the selected memory cell, and compare data read out by successive two data read operations with each other so as to judge a threshold margin of the selected memory cell.

Abstract translation: 非易失性半导体存储器件包括：具有布置在其中的电可重写和非易失性存储单元的单元阵列; 以及读出放大器电路，被配置为检测所述单元阵列中的位线的电压变化，从而读取耦合到所述位线的所选存储单元的数据，其中所述读出放大器电路被控制为在多个定时内在 位线电压与所选择的存储单元相对应地变化，并且通过连续两个数据读取操作读出的数据彼此进行比较，以便判断所选存储单元的阈值余量。

公开(公告)号：US06826068B1

公开(公告)日：2004-11-30

申请号：US10654463

申请日：2003-09-03

Applicant: Hitoshi Shiga ,  Yoshinori Takano ,  Toru Tanzawa ,  Shigeru Atsumi

Inventor： Hitoshi Shiga ,  Yoshinori Takano ,  Toru Tanzawa ,  Shigeru Atsumi

IPC: G11C506

CPC classification number: G11C7/1021 ,  G11C8/10

Abstract: A semiconductor integrated circuit device includes first to fourth bit lines and a redundant bit line, first to fourth column gate transistors and a redundant column gate transistor coupled to each of the first to fourth bit lines and the redundant bit lines, first to fourth column select lines and a redundant column select line coupled to each of the first to fourth column gate transistors and the redundant column gate transistor. The second column select line passes through the first bit line. The third column select line passes through the first and second bit lines. The fourth column select line passes through the first, second and third bit lines. The redundant column select line passes through the first, second, third and fourth bit lines.

Abstract translation: 半导体集成电路器件包括第一至第四位线和冗余位线，第一至第四列栅极晶体管和耦合到第一至第四位线和冗余位线中的每一个的冗余列栅极晶体管，第一至第四列选择 线路以及耦合到第一至第四列栅极晶体管和冗余列栅极晶体管中的每一个的冗余列选择线。 第二列选择线通过第一位线。 第三列选择线通过第一和第二位线。 第四列选择线通过第一，第二和第三位线。 冗余列选择线通过第一，第二，第三和第四位线。

公开(公告)号：US06434054B1

公开(公告)日：2002-08-13

申请号：US10040383

申请日：2002-01-09

Applicant: Hitoshi Shiga ,  Toru Tanzawa ,  Masanobu Saito

Inventor： Hitoshi Shiga ,  Toru Tanzawa ,  Masanobu Saito

IPC: G11C1616

CPC classification number: G11C16/3409 ,  G11C16/16 ,  G11C16/3404 ,  G11C2216/20

Abstract: A non-volatile semiconductor memory device according to the invention comprises a memory cell array having a plurality of non-volatile memory cells, and a write state machine controlling a voltage applied to a memory cell selected from the memory cell array and a voltage application period, in accordance with each of reading of data from the selected memory cell, writing of data into the selected memory cell, and erasion of data from the selected memory. The write state machine executes writing, under a first writing condition, on a predetermined number of memory cells included in the memory cell array, and executes writing on memory cells other than the predetermined number of memory cells, under a second writing condition set in accordance with a result of the writing executed under the first writing condition.

Abstract translation: 根据本发明的非易失性半导体存储器件包括具有多个非易失性存储单元的存储单元阵列，以及控制施加到从存储单元阵列选择的存储单元的电压的写状态机和施加电压的周期 根据从所选择的存储器单元读取数据的每一个，将数据写入所选存储单元，以及从所选存储器中擦除数据。 写入状态机在第一写入条件下执行包含在存储单元阵列中的预定数量的存储单元上的写入，并且在按照相应设置的第二写入条件下执行对除了预定数量的存储单元之外的存储单元的写入 其结果是在第一写入条件下执行写入。

公开(公告)号：US06351417B1

公开(公告)日：2002-02-26

申请号：US09833687

申请日：2001-04-13

Applicant: Hitoshi Shiga ,  Toru Tanzawa ,  Masanobu Saito

Inventor： Hitoshi Shiga ,  Toru Tanzawa ,  Masanobu Saito

IPC: G11C1616

CPC classification number: G11C16/3409 ,  G11C16/16 ,  G11C16/3404 ,  G11C2216/20

Abstract: A non-volatile semiconductor memory device according to the invention comprises a memory cell array having a plurality of non-volatile memory cells, and a write state machine controlling a voltage applied to a memory cell selected from the memory cell array and a voltage application period, in accordance with each of reading of data from the selected memory cell, writing of data into the selected memory cell, and erasing of data from the selected memory. The write state machine executes writing, under a first writing condition, on a predetermined number of memory cells included in the memory cell array, and executes writing on memory cells other than the predetermined number of memory cells, under a second writing condition set in accordance with a result of the writing executed under the first writing condition.

Abstract translation: 根据本发明的非易失性半导体存储器件包括具有多个非易失性存储单元的存储单元阵列，以及控制施加到从存储单元阵列选择的存储单元的电压的写状态机和施加电压的周期 根据从所选存储单元读取数据的每一个，将数据写入所选存储单元，以及从所选存储器擦除数据。 写入状态机在第一写入条件下执行包含在存储单元阵列中的预定数量的存储单元上的写入，并且在按照相应设置的第二写入条件下执行对除了预定数量的存储单元之外的存储单元的写入 其结果是在第一写入条件下执行写入。

公开(公告)号：US6041012A

公开(公告)日：2000-03-21

申请号：US31686

申请日：1998-02-27

Applicant: Hironori Banba ,  Hitoshi Shiga ,  Shigeru Atsumi ,  Akira Umezawa

Inventor： Hironori Banba ,  Hitoshi Shiga ,  Shigeru Atsumi ,  Akira Umezawa

IPC: G11C5/14 ,  G11C16/30 ,  G11C7/00

CPC classification number: G11C5/143 ,  G11C16/30 ,  G11C5/145 ,  G11C5/147

Abstract: A semiconductor integrated circuit device according to the present invention includes a booster circuit 1 for raising an external power supply voltage Vccext, a level detecting circuit 2 for detecting fluctuation in a stepped-up voltage Vccint2, an internal voltage generating circuit 3 for generating an internal voltage Vccint on the basis of the stepped-up voltage Vccint2, an address buffer 4, an address decoder 5, and a memory cell array 6 of an EEPROM structure. The level detecting circuit 2 includes a first level detecting part for performing level detection during a memory access state, and a second level detecting part for performing level detection during a stand-by state. During the stand-by state, the internal voltage generating circuit 3 short-circuits the stepped-up voltage Vccint2 and the internal voltage Vccint. The second level detecting part has lower power consumption than that of the first level detecting part, so that it is possible to reducing the power consumption during the stand-by state without lowering the driving voltage.

Abstract translation: 根据本发明的半导体集成电路器件包括用于提高外部电源电压Vccext的升压电路1，用于检测升压电压Vccint2中的波动的电平检测电路2，用于产生内部电压的内部电压产生电路3 基于升压电压Vccint2的电压Vccint，地址缓冲器4，地址解码器5和EEPROM结构的存储单元阵列6。 电平检测电路2包括用于在存储器访问状态期间执行电平检测的第一电平检测部分和用于在待机状态期间执行电平检测的第二电平检测部分。 在待机状态下，内部电压产生电路3使升压电压Vccint2和内部电压Vccint短路。 第二电平检测部件具有比第一电平检测部件低的功率消耗，从而可以在不降低驱动电压的情况下降低待机状态下的功耗。