公开(公告)号：US20070115746A1

公开(公告)日：2007-05-24

申请号：US11623569

申请日：2007-01-16

Applicant: Jae Im ,  Jae-jin Lee

Inventor： Jae Im ,  Jae-jin Lee

IPC: G11C5/14

CPC classification number: G11C5/14 ,  G11C11/406 ,  G11C11/4074 ,  G11C2211/4068

Abstract: Disclosed herein is an internal voltage generation circuit of a semiconductor memory device which is capable of supplying voltages of different levels to a column path & control logic and data path & control logic in the memory device according to different operation modes of the memory device. The column path & control logic and data path & control logic are applied with a normal operating voltage when they are involved in the current operation mode of the memory device, whereas with a lower voltage when they are not involved. Therefore, the present invention has the effect of efficiently managing internal voltages of the semiconductor memory device and reducing current leakage of the memory device and, in turn, unnecessary power consumption thereof.

Abstract translation: 本文公开了一种半导体存储器件的内部电压产生电路，其能够根据存储器件的不同操作模式向存储器件中的列路径和控制逻辑以及数据路径和控制逻辑提供不同电平的电压。 列路径和控制逻辑以及数据路径和控制逻辑在其参与存储器件的当前操作模式时被应用于正常工作电压，而当它们不涉及时具有较低的电压。 因此，本发明具有有效地管理半导体存储器件的内部电压并且减少存储器件的电流泄漏的效果，并且反过来又导致其不必要的功耗。

公开(公告)号：US20070070743A1

公开(公告)日：2007-03-29

申请号：US11541236

申请日：2006-09-28

Applicant: Chang-Ho Do ,  Jae-Jin Lee

Inventor： Chang-Ho Do ,  Jae-Jin Lee

IPC: G11C29/00

CPC classification number: G11C29/26 ,  G11C8/16

Abstract: A semiconductor memory device includes: a plurality of ports configured to perform a serial input/output (I/O) data communication with external devices; a plurality of banks configured to perform a parallel I/O data communication with the ports; a global data bus configured to transmit a signal between the banks and the ports; a test mode determiner configured to determine an operation mode of the semiconductor memory device by generating a test mode enable signal in response to a test mode control signal; a test I/O controller configured to transmit and receive a test signal with the ports in response to the test mode enable signal during a port test mode; and a plurality of selectors, each of which is configured to receive the test signal output from the corresponding port in series and feedback the test signal to the corresponding port.

Abstract translation: 半导体存储器件包括：多个端口，被配置为执行与外部设备的串行输入/输出（I / O）数据通信; 配置为执行与所述端口的并行I / O数据通信的多个存储体; 全局数据总线，被配置为在所述存储体和所述端口之间传输信号; 测试模式确定器，被配置为通过响应于测试模式控制信号产生测试模式使能信号来确定半导体存储器件的操作模式; 测试I / O控制器，被配置为在端口测试模式期间响应于测试模式使能信号在端口上发送和接收测试信号; 以及多个选择器，每个选择器被配置为从串行的相应端口接收输出的测试信号，并将测试信号反馈到相应的端口。

公开(公告)号：US20070070720A1

公开(公告)日：2007-03-29

申请号：US11478192

申请日：2006-06-30

Applicant: Kang-Seol Lee ,  Jae-Jin Lee

Inventor： Kang-Seol Lee ,  Jae-Jin Lee

IPC: G11C5/14

CPC classification number: G11C5/14

Abstract: A voltage generator for use in a semiconductor memory device includes an output voltage controller for generating a bias voltage using a reference voltage of which a voltage level is half of a core voltage level. Pull-up/pull-down driving signals are output by generating a voltage which is higher or lower than the reference voltage by a threshold voltage. An output driver generates a bit line precharge voltage in response to the pull-up driving signal or the pull-down driving signal. Drive controllers interrupt off-leakage current of the output driver. One drive controller is disposed between the output driver and a core voltage terminal and another drive controller is between the output driver and a ground voltage terminal.

Abstract translation: 用于半导体存储器件的电压发生器包括：输出电压控制器，用于使用电压电平为核心电压电平的一半的参考电压产生偏置电压。 通过产生高于或低于参考电压阈值电压的电压来输出上拉/下拉驱动信号。 输出驱动器响应于上拉驱动信号或下拉驱动信号产生位线预充电电压。 驱动控制器会中断输出驱动器的漏电流。 一个驱动控制器设置在输出驱动器和核心电压端子之间，另一个驱动控制器位于输出驱动器和地电压端子之间。

公开(公告)号：US07139211B2

公开(公告)日：2006-11-21

申请号：US11017683

申请日：2004-12-22

Applicant: Dong-Keun Kim ,  Jae-Jin Lee

Inventor： Dong-Keun Kim ,  Jae-Jin Lee

IPC: G11C8/00

CPC classification number: G11C7/1069 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/18 ,  G11C2207/105

Abstract: A semiconductor memory device with a reduced cell area and a high-speed data transfer by modifying a circuit layout. The semiconductor memory device includes: a cell area with a first and a second cell areas; a plurality of Y decoders of which one Y decoder selects bit line sense amplifiers in the first and the second cell areas; IO sense amplifiers provided with a first IO sense amplifier and a second IO sense amplifier; a plurality of first data lines for transferring a data sensed and amplified at the bit line sense amplifier of the first cell area; and a plurality of second data lines for transferring a data sensed and amplified at the bit line sense amplifier of the second cell area.

公开(公告)号：US07106640B2

公开(公告)日：2006-09-12

申请号：US11024902

申请日：2004-12-30

Applicant: Seok-Cheol Yoon ,  Jae-Jin Lee

Inventor： Seok-Cheol Yoon ,  Jae-Jin Lee

IPC: G11C7/00

CPC classification number: G11C29/027 ,  G11C29/24 ,  G11C29/781 ,  G11C2029/4402

Abstract: There is provided a semiconductor memory device capable of detecting a repaired address in a test mode. The semiconductor memory device includes: a plurality of unit address detectors for comparing 1-bit address signal with a stored 1-bit repair address signal to output a repair signal, and for buffering the stored repair address signal and outputting the buffered repair address signal as the repair signal in a test mode; a redundancy address detector for combining the plurality of repair signals from the unit address detectors and outputting a detection signal for detecting whether a current input address is a redundancy address; and a redundancy flag signal generator for generating a redundancy flag signal in response to the detection signal and transferring the redundancy flag signal to a data output path.

Abstract translation: 提供了能够在测试模式下检测修复的地址的半导体存储器件。 半导体存储器件包括：多个单元地址检测器，用于将1位地址信号与存储的1位修复地址信号进行比较，以输出修复信号，并用于缓存存储的修复地址信号，并将缓冲的修复地址信号作为 修复信号处于测试模式; 冗余地址检测器，用于组合来自单元地址检测器的多个修复信号，并输出用于检测当前输入地址是否为冗余地址的检测信号; 以及冗余标志信号发生器，用于响应于检测信号产生冗余标志信号，并将冗余标志信号传送到数据输出路径。

公开(公告)号：US07098712B2

公开(公告)日：2006-08-29

申请号：US10858976

申请日：2004-06-01

Applicant: Jae-Jin Lee

Inventor： Jae-Jin Lee

IPC: H03L7/00

CPC classification number: H03L7/0805 ,  H03L7/0814 ,  H03L7/093

Abstract: A register controlled delay locked loop includes a clock generation unit which receives an external clock signal for generating a source clock signal by buffering the external clock signal and for generating a delay monitoring clock signal and a reference clock signal by diving the source clock signal by a natural number; a delay line control unit which receives the reference clock signal and a feed-backed clock signal for generating a normal shift control signal and an acceleration shift control signal based on a result of a comparison between phases of the reference clock signal and the feed-backed clock signal; a delay line unit which receives the source clock signal for generating a delay locked clock signal by delaying the source clock signal according to a delay amount of the delay line unit determined by the normal shift control signal and the acceleration shift control signal; and a delay model unit for estimating a delay amount generated while the external clock signal is passed to a data output pin to generate the feed-backed clock signal, wherein an absolute delay amount based on the acceleration shift control signal is larger than that based on the normal shift control signal.

Abstract translation: 寄存器控制的延迟锁定环包括时钟产生单元，其通过缓冲外部时钟信号来接收用于产生源时钟信号的外部时钟信号，并且通过将源时钟信号通过将源时钟信号进行潜水来产生延迟监视时钟信号和参考时钟信号 自然数; 延迟线控制单元，其接收参考时钟信号和用于产生正常移位控制信号的反馈时钟信号和加速移位控制信号，该信号基于参考时钟信号和反馈回路的相位之间的比较结果 时钟信号; 延迟线单元，其通过根据由正常移位控制信号和加速度移位控制信号确定的延迟线单元的延迟量延迟源时钟信号来接收用于产生延迟锁定时钟信号的源时钟信号; 以及延迟模型单元，用于估计在外部时钟信号被传递到数据输出引脚时产生的延迟量以产生反馈时钟信号，其中基于加速度移位控制信号的绝对延迟量大于基于 正常换档控制信号。

公开(公告)号：US07016255B2

公开(公告)日：2006-03-21

申请号：US10876231

申请日：2004-06-23

Applicant: Ihl-Ho Lee ,  Kyung-Whan Kim ,  Jae-Jin Lee

Inventor： Ihl-Ho Lee ,  Kyung-Whan Kim ,  Jae-Jin Lee

IPC: G11C7/00

CPC classification number: G11C7/1075 ,  G11C8/16 ,  G11C11/4097 ,  G11C29/846 ,  G11C2207/002

Abstract: A multi-port memory device can avoid failure of the first high data during initial operation so that reliability and operation characteristic of the memory device can be improved. The multi-port memory device comprises a global data bus having a multiplicity of bus lines, a plurality of banks having a current sensing type transceiving structure for exchanging data with the global data bus, one or more ports having a current sensing type transceiving structure for exchanging data with the global data bus, a plurality of switches, each arranged between the corresponding bank and the bus lines of the global data bus for selectively connecting one of a redundant column and normal columns of the corresponding bank to the global data bus, and a controlling unit for restricting the turn-on period of the switches to the substantial operation period of the corresponding bank.

Abstract translation: 多端口存储器件可以避免初始操作期间第一高数据的故障，从而可以提高存储器件的可靠性和操作特性。 多端口存储器件包括具有多条总线线路的全局数据总线，多个存储体具有用于与全局数据总线交换数据的电流检测型收发结构，具有电流检测型收发结构的一个或多个端口 与全局数据总线交换数据，多个开关，每个交换机布置在全局数据总线的对应组和总线之间，用于选择性地将对应组的冗余列和正常列之一连接到全局数据总线;以及 控制单元，用于将开关的导通周期限制到相应银行的实质操作周期。

公开(公告)号：US20050225379A1

公开(公告)日：2005-10-13

申请号：US10982165

申请日：2004-11-05

Applicant: Jae-Hyuk Im ,  Jae-Jin Lee

Inventor： Jae-Hyuk Im ,  Jae-Jin Lee

IPC: G11C5/14 ,  G11C7/00 ,  G11C11/4063 ,  G11C11/4074 ,  G11C11/413 ,  H03L5/00

CPC classification number: G11C5/14 ,  G11C11/406 ,  G11C11/4074 ,  G11C2211/4068

Abstract: Disclosed herein is an internal voltage generation circuit of a semiconductor memory device which is capable of supplying voltages of different levels to a column path & control logic and data path & control logic in the memory device according to different operation modes of the memory device. The column path & control logic and data path & control logic are applied with a normal operating voltage when they are involved in the current operation mode of the memory device, whereas with a lower voltage when they are not involved. Therefore, the present invention has the effect of efficiently managing internal voltages of the semiconductor memory device and reducing current leakage of the memory device and, in turn, unnecessary power consumption thereof.

Abstract translation: 本文公开了一种半导体存储器件的内部电压产生电路，其能够根据存储器件的不同操作模式向存储器件中的列路径和控制逻辑以及数据路径和控制逻辑提供不同电平的电压。 列路径和控制逻辑以及数据路径和控制逻辑在其参与存储器件的当前操作模式时被应用于正常工作电压，而当它们不涉及时具有较低的电压。 因此，本发明具有有效地管理半导体存储器件的内部电压并且减少存储器件的电流泄漏的效果，并且反过来又导致其不必要的功耗。

公开(公告)号：US06943585B2

公开(公告)日：2005-09-13

申请号：US10694966

申请日：2003-10-28

Applicant: Jae Jin Lee ,  Kang Seol Lee

Inventor： Jae Jin Lee ,  Kang Seol Lee

IPC: H03K19/018 ,  G11C7/10 ,  H03K19/00 ,  H03K19/0948

CPC classification number: G11C7/1078 ,  G11C7/1084 ,  G11C2207/2227 ,  H03K19/0016

Abstract: Disclosed is an input apparatus used in a SSTL interface, which comprises a differential buffer for comparing an external input signal with a reference potential inputted from an external, and a CMOS buffer for buffering the external input signal. In the input apparatus, the CMOS buffer operates when a command signal or an address signal is not inputted from an external, and when a predetermined operation such as a refresh operation is performed, thereby reducing the power consumption in a standby mode. Further, in order to prevent the input apparatus from abnormally operating when the reference potential is not maintained in the normal operation range, a reference potential level detecting circuit is further included in the input apparatus, so that the CMOS buffer operates when the reference potential deviates from a predetermined normal operation range. Furthermore, in order to enable an input buffer to operate as the CMOS when an input signal fully swings, a circuit for detecting a potential of an input signal inputted from an external is further included in the input apparatus.

Abstract translation: 公开了一种在SSTL接口中使用的输入装置，其包括用于将外部输入信号与从外部输入的参考电位进行比较的差分缓冲器和用于缓冲外部输入信号的CMOS缓冲器。 在输入装置中，当没有从外部输入命令信号或地址信号时，并且当执行诸如刷新操作的预定操作时，CMOS缓冲器操作，从而降低待机模式下的功耗。 此外，为了防止输入装置在基准电位不保持在正常工作范围时异常工作，在输入装置中还包括基准电位电平检测电路，使得CMOS缓冲器在参考电位偏移 从预定的正常操作范围。 此外，为了使输入缓冲器在输入信号完全摆动时作为CMOS工作，在输入装置中还包括用于检测从外部输入的输入信号的电位的电路。

公开(公告)号：US06940325B2

公开(公告)日：2005-09-06

申请号：US10672990

申请日：2003-09-26

Applicant: Jae Jin Lee

Inventor： Jae Jin Lee

IPC: G11C11/407 ,  H03L7/06 ,  H03L7/081

CPC classification number: H03L7/0805 ,  H03L7/0814

Abstract: A DLL circuit synchronizes an external input clock applied from an outside of a system with an internal input clock used inside the system using a divider unit. The DLL circuit includes a detection unit for detecting whether a pulse width of the external input clock is narrower than a reference set value. The divider unit outputs a first divided signal when it is detected that the pulse width of the external input clock is wider than the reference set value, and outputs a second divided signal when it is detected that the pulse width of the external input clock is shorter than the reference set value. The DLL circuit can normally operate even when the period of the external input clock is short.

Abstract translation: DLL电路使用分频器单元将从系统外部施加的外部输入时钟与系统内部使用的内部输入时钟同步。 DLL电路包括检测单元，用于检测外部输入时钟的脉冲宽度是否比参考设定值窄。 当检测到外部输入时钟的脉冲宽度大于参考设定值时，除法器单元输出第一分频信号，并且当检测到外部输入时钟的脉冲宽度较短时输出第二分频信号 比参考设定值。 即使当外部输入时钟的周期短时，DLL电路也可以正常工作。