公开(公告)号：US07439596B2

公开(公告)日：2008-10-21

申请号：US11045060

申请日：2005-01-31

Applicant: Jae-Yoon Yoo ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee ,  Hyun-Suk Kim ,  Moon-Han Park

Inventor： Jae-Yoon Yoo ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee ,  Hyun-Suk Kim ,  Moon-Han Park

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/66537 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present invention discloses a transistor for a semiconductor device capable of preventing the generation of a depletion capacitance in a gate pattern due to the diffusion of impurity ions. The present invention also discloses a method of fabricating the transistor.

Abstract translation: 本发明公开了一种用于半导体器件的晶体管，其能够防止由于杂质离子的扩散而产生栅极图案中的耗尽电容。 本发明还公开了一种制造晶体管的方法。

公开(公告)号：US20080242010A1

公开(公告)日：2008-10-02

申请号：US12149329

申请日：2008-04-30

Applicant: Hwa-Sung Rhee ,  Hyun-Suk Kim ,  Ueno Tetsuji ,  Jae-Yoon Yoo ,  Seung-Hwan Lee ,  Ho Lee ,  Moon-han Park

Inventor： Hwa-Sung Rhee ,  Hyun-Suk Kim ,  Ueno Tetsuji ,  Jae-Yoon Yoo ,  Seung-Hwan Lee ,  Ho Lee ,  Moon-han Park

IPC: H01L21/336

CPC classification number: H01L29/7853 ,  H01L29/66795

Abstract: An at least penta-sided-channel type of FinFET transistor may include: a base; a semiconductor body formed on the base, the body being arranged in a long dimension to have source/drain regions sandwiching a channel region, at least the channel, in cross-section transverse to the long dimension, having at least five planar surfaces above the base; a gate insulator on the channel region of the body; and a gate electrode formed on the gate insulator.

Abstract translation: 至少五面通道类型的FinFET晶体管可以包括：基极; 形成在所述基座上的半导体本体，所述主体被布置成较长的尺寸，以使源极/漏极区域夹持沟道区域，至少所述沟道横截面与所述长尺寸的横截面具有至少五个平面 基础; 主体通道区上的栅极绝缘体; 以及形成在栅极绝缘体上的栅电极。

公开(公告)号：US20050156202A1

公开(公告)日：2005-07-21

申请号：US10986018

申请日：2004-11-12

Applicant: Hwa-Sung Rhee ,  Hyun-Suk Kim ,  Ueno Tetsuji ,  Jae-Yoon Yoo ,  Seung-Hwan Lee ,  Ho Lee ,  Moon-han Park

Inventor： Hwa-Sung Rhee ,  Hyun-Suk Kim ,  Ueno Tetsuji ,  Jae-Yoon Yoo ,  Seung-Hwan Lee ,  Ho Lee ,  Moon-han Park

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76 ,  H01L21/00

CPC classification number: H01L29/7853 ,  H01L29/66795

Abstract: An at least penta-sided-channel type of FinFET transistor may include: a base; a semiconductor body formed on the base, the body being arranged in a long dimension to have source/drain regions sandwiching a channel region, at least the channel, in cross-section transverse to the long dimension, having at least five planar surfaces above the base; a gate insulator on the channel region of the body; and a gate electrode formed on the gate insulator.

Abstract translation: 至少五面通道类型的FinFET晶体管可以包括：基极; 形成在所述基座上的半导体本体，所述主体被布置成较长的尺寸，以使源极/漏极区域夹持沟道区域，至少所述沟道横截面与所述长尺寸的横截面具有至少五个平面 基础; 主体通道区上的栅极绝缘体; 以及形成在栅极绝缘体上的栅电极。

公开(公告)号：US06878575B2

公开(公告)日：2005-04-12

申请号：US10727125

申请日：2003-12-03

Applicant: Jae-Yoon Yoo ,  Moon-Han Park ,  Byou-Ree Lim

Inventor： Jae-Yoon Yoo ,  Moon-Han Park ,  Byou-Ree Lim

IPC: H01L21/31 ,  H01L21/28 ,  H01L21/314 ,  H01L29/51 ,  H01L21/335

CPC classification number: H01L21/28202 ,  H01L21/3144 ,  H01L29/513 ,  H01L29/518

Abstract: Methods of preparing improved semiconductor substrates having gate oxide layers formed thereon, and use of such substrates in fabricating improved semiconductor devices, are disclosed. The methods include a first step of performing a cleaning process for removing a natural oxide layer formed on a semiconductor substrate and also for removing an oxide layer generated by the removal of the natural oxide layer; a second step of executing a hydrogen annealing process to form a hydrogen passivation layer and for further reducing a surface roughness of the semiconductor substrate completed in the cleaning process; a third step of forming a gate oxide layer thereon; a fourth step of performing a nitridation process on the gate oxide layer to prevent the semiconductor substrate from a permeation of ions during a subsequent gate electrode formation step; and, a fifth step of performing a subsequent thermal process to stabilize a surface of the gate oxide layer, thereby improving a defect rate of the device caused in forming the gate oxide layer.

Abstract translation: 公开了制备其上形成有栅氧化层的改进的半导体衬底的方法，以及这些衬底在制造改进的半导体器件中的用途。 所述方法包括进行用于去除形成在半导体衬底上的自然氧化物层的清洁工艺以及去除通过除去天然氧化物层而产生的氧化物层的第一步骤; 执行氢退火处理以形成氢钝化层并进一步降低在清洁过程中完成的半导体衬底的表面粗糙度的第二步骤; 在其上形成栅氧化层的第三步骤; 在栅极氧化层上进行氮化处理以防止半导体衬底在随后的栅电极形成步骤期间渗透离子的第四步骤; 以及进行后续热处理以稳定栅极氧化物层的表面的第五步骤，从而提高在形成栅极氧化物层时引起的器件的缺陷率。