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    Method of forming gate oxide layer in semiconductor devices
    1.
    发明授权
    Method of forming gate oxide layer in semiconductor devices 有权
    在半导体器件中形成栅氧化层的方法

    公开(公告)号：US06878575B2

    公开(公告)日：2005-04-12

    申请号：US10727125

    申请日：2003-12-03

    申请人： Jae-Yoon Yoo ,  Moon-Han Park ,  Byou-Ree Lim

    发明人： Jae-Yoon Yoo ,  Moon-Han Park ,  Byou-Ree Lim

    IPC分类号： H01L21/31 ,  H01L21/28 ,  H01L21/314 ,  H01L29/51 ,  H01L21/335

    CPC分类号： H01L21/28202 ,  H01L21/3144 ,  H01L29/513 ,  H01L29/518

    摘要： Methods of preparing improved semiconductor substrates having gate oxide layers formed thereon, and use of such substrates in fabricating improved semiconductor devices, are disclosed. The methods include a first step of performing a cleaning process for removing a natural oxide layer formed on a semiconductor substrate and also for removing an oxide layer generated by the removal of the natural oxide layer; a second step of executing a hydrogen annealing process to form a hydrogen passivation layer and for further reducing a surface roughness of the semiconductor substrate completed in the cleaning process; a third step of forming a gate oxide layer thereon; a fourth step of performing a nitridation process on the gate oxide layer to prevent the semiconductor substrate from a permeation of ions during a subsequent gate electrode formation step; and, a fifth step of performing a subsequent thermal process to stabilize a surface of the gate oxide layer, thereby improving a defect rate of the device caused in forming the gate oxide layer.

    摘要翻译： 公开了制备其上形成有栅氧化层的改进的半导体衬底的方法，以及这些衬底在制造改进的半导体器件中的用途。 所述方法包括进行用于去除形成在半导体衬底上的自然氧化物层的清洁工艺以及去除通过除去天然氧化物层而产生的氧化物层的第一步骤; 执行氢退火处理以形成氢钝化层并进一步降低在清洁过程中完成的半导体衬底的表面粗糙度的第二步骤; 在其上形成栅氧化层的第三步骤; 在栅极氧化层上进行氮化处理以防止半导体衬底在随后的栅电极形成步骤期间渗透离子的第四步骤; 以及进行后续热处理以稳定栅极氧化物层的表面的第五步骤，从而提高在形成栅极氧化物层时引起的器件的缺陷率。

    Multi-layered structure including an epitaxial layer having a low dislocation defect density, semiconductor device comprising the same, and method of fabricating the semiconductor device
    3.
    发明授权
    Multi-layered structure including an epitaxial layer having a low dislocation defect density, semiconductor device comprising the same, and method of fabricating the semiconductor device 有权
    包括具有低位错缺陷密度的外延层的多层结构以及包含该外延层的半导体器件以及制造该半导体器件的方法

    公开(公告)号：US06987310B2

    公开(公告)日：2006-01-17

    申请号：US10851336

    申请日：2004-05-24

    申请人： Ho Lee ,  Moon-Han Park ,  Hwa-Sung Rhee ,  Jae-Yoon Yoo ,  Seung-Hwan Lee

    发明人： Ho Lee ,  Moon-Han Park ,  Hwa-Sung Rhee ,  Jae-Yoon Yoo ,  Seung-Hwan Lee

    IPC分类号： H01L31/328 ,  H01L31/72 ,  H01L31/336 ,  H01L31/109 ,  H01L39/60

    CPC分类号： H01L21/02532 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/0251

    摘要： A multi-layered structure of a semiconductor device includes a substrate, and a heteroepitaxial layer having a low dislocation defect density on the substrate. The heteroepitaxial layer consists of a main epitaxial layer and at least one intermediate epitaxial layer sandwished in the main epitaxial layer. At their interface, the heteroepitaxial layer, i.e., the bottom portion of the main epitaxial layer, and the substrate have different lattice constants. Also, the intermediate epitaxial layer has a different lattice constant from that of the portions of the main epitaxial layer contiguous to the intermediate epitaxial layer. The intermediate epitaxial layer also has a thickness smaller than the net thickness of the main epitaxial layer such that the intermediate epitaxial layer absorbs the strain in the heteroepitaxial layer. Thus, it is possible to obtain a multi-layered structure comprising an epitaxial layer that is relatively thin and has a low dislocation defect density.

    摘要翻译： 半导体器件的多层结构包括衬底和在衬底上具有低位错缺陷密度的异质外延层。 异质外延层由主外延层和在外延层中形成的至少一个中间外延层组成。 在其界面处，异质外延层，即主外延层的底部，以及基板具有不同的晶格常数。 此外，中间外延层具有与与外延层相邻的主外延层的部分的晶格常数不同的晶格常数。 中间外延层的厚度也小于主外延层的净厚度，使得中间外延层吸收异质外延层中的应变。 因此，可以获得包括相对薄且具有低位错缺陷密度的外延层的多层结构。

    Multi-layered structure including an epitaxial layer having a low dislocation defect density, semiconductor device comprising the same, and method of fabricating the semiconductor device
    4.
    发明申请
    Multi-layered structure including an epitaxial layer having a low dislocation defect density, semiconductor device comprising the same, and method of fabricating the semiconductor device 审中-公开
    包括具有低位错缺陷密度的外延层的多层结构以及包含该外延层的半导体器件以及制造该半导体器件的方法

    公开(公告)号：US20050274981A1

    公开(公告)日：2005-12-15

    申请号：US11194529

    申请日：2005-08-02

    申请人： Ho Lee ,  Moon-Han Park ,  Hwa-Sung Rhee ,  Jae-Yoon Yoo ,  Seung-Hwan Lee

    发明人： Ho Lee ,  Moon-Han Park ,  Hwa-Sung Rhee ,  Jae-Yoon Yoo ,  Seung-Hwan Lee

    IPC分类号： H01L21/20 ,  H01L21/8238 ,  H01L31/072 ,  H01L31/117

    CPC分类号： H01L21/02532 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/0251

    摘要： A multi-layered structure of a semiconductor device includes a substrate, and a heteroepitaxial layer having a low dislocation defect density on the substrate. The heteroepitaxial layer consists of a main epitaxial layer and at least one intermediate epitaxial layer sandwished in the main epitaxial layer. At their interface, the heteroepitaxial layer, i.e., the bottom portion of the main epitaxial layer, and the substrate have different lattice constants. Also, the intermediate epitaxial layer has a different lattice constant from that of the portions of the main epitaxial layer contiguous to the intermediate epitaxial layer. The intermediate epitaxial layer also has a thickness smaller than the net thickness of the main epitaxial layer such that the intermediate epitaxial layer absorbs the strain in the heteroepitaxial layer. Thus, it is possible to obtain a multi-layered structure comprising an epitaxial layer that is relatively thin and has a low dislocation defect density.

    摘要翻译： 半导体器件的多层结构包括衬底和在衬底上具有低位错缺陷密度的异质外延层。 异质外延层由主外延层和在外延层中形成的至少一个中间外延层组成。 在其界面处，异质外延层，即主外延层的底部，以及基板具有不同的晶格常数。 此外，中间外延层具有与与外延层相邻的主外延层的部分的晶格常数不同的晶格常数。 中间外延层的厚度也小于主外延层的净厚度，使得中间外延层吸收异质外延层中的应变。 因此，可以获得包括相对薄且具有低位错缺陷密度的外延层的多层结构。

    Multi-layered structure including an epitaxial layer having a low dislocation defect density, semiconductor device comprising the same, and method of fabricating the semiconductor device
    7.
    发明申请
    Multi-layered structure including an epitaxial layer having a low dislocation defect density, semiconductor device comprising the same, and method of fabricating the semiconductor device 有权
    包括具有低位错缺陷密度的外延层的多层结构以及包含该外延层的半导体器件以及制造该半导体器件的方法

    公开(公告)号：US20050023646A1

    公开(公告)日：2005-02-03

    申请号：US10851336

    申请日：2004-05-24

    申请人： Ho Lee ,  Moon-Han Park ,  Hwa-Sung Rhee ,  Jae-Yoon Yoo ,  Seung-Hwan Lee

    发明人： Ho Lee ,  Moon-Han Park ,  Hwa-Sung Rhee ,  Jae-Yoon Yoo ,  Seung-Hwan Lee

    IPC分类号： H01L21/20 ,  H01L21/8238 ,  H01L31/072 ,  H01L31/117

    CPC分类号： H01L21/02532 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/0251

    摘要： A multi-layered structure of a semiconducotr device includes a substrate, and a heteroepitaxial layer having a low dislocation defect density on the substrate. The heteroepitaxial layer consists of a main epitaxial layer and at least one intermediate epitaxial layer sandwished in the main epitaxial layer. At their interface, the heteroepitaxial layer, i.e., the bottom portion of the main epitaxial layer, and the substrate have different lattice constants. Also, the intermediate epitaxial layer has a different lattice constant from that of the portions of the main epitaxial layer contiguous to the intermediate epitaxial layer. The intermediate epitaxial layer also has a thickness smaller than the net thickness of the main epitaxial layer such that the intermediate epitaxial layer absorbs the strain in the heteroepitaxial layer. Thus, it is possible to obtain a multi-layered structure comprising an epitaxial layer that is relatively thin and has a low dislocation defect density.

    摘要翻译： 半导体器件的多层结构包括衬底和在衬底上具有低位错缺陷密度的异质外延层。 异质外延层由主外延层和在外延层中形成的至少一个中间外延层组成。 在其界面处，异质外延层，即主外延层的底部，以及基板具有不同的晶格常数。 此外，中间外延层具有与与外延层相邻的主外延层的部分的晶格常数不同的晶格常数。 中间外延层的厚度也小于主外延层的净厚度，使得中间外延层吸收异质外延层中的应变。 因此，可以获得包括相对薄且具有低位错缺陷密度的外延层的多层结构。