Tri-state output logic with zero quiescent current by one input control
    21.
    发明申请
    Tri-state output logic with zero quiescent current by one input control 失效
    具有零静态电流的三态输出逻辑由一个输入控制

    公开(公告)号:US20060279331A1

    公开(公告)日:2006-12-14

    申请号:US11217341

    申请日:2005-09-02

    CPC classification number: G06F1/26

    Abstract: A voltage generating circuit, which generates tri-state logic output in accordance with high, low or floating of the input node, is proposed. The present voltage generating circuit includes: a pulse generating circuit for generating a plurality of pulses; a voltage selecting circuit having a pair of NMOS transistors coupled in common source, each drain of the NMOS transistors is coupled to a current source respectively, both gates of the NMOS transistors are coupled to an input node, and the paired drain of the NMOS transistors generate a pair of voltage output; a plurality of flip-flops, which couple to drains of the NMOS transistors to lock the voltage output of the NMOS transistors in accordance with the pulses; an inner voltage-generating unit couples to the input node for providing a floating voltage level; and a plurality of switches controlled by the pulses for controlling the normal operation of the voltage selecting circuit and the conduction between the inner-voltage generating unit with the input node.

    Abstract translation: 提出了根据输入节点的高,低或浮动产生三态逻辑输出的电压产生电路。 本电压发生电路包括:产生多个脉冲的脉冲发生电路; 一个电压选择电路,具有耦合在公共源极上的一对NMOS晶体管,NMOS晶体管的每个漏极分别耦合到电流源,NMOS晶体管的两个栅极耦合到输入节点,并且NMOS晶体管的成对漏极 产生一对电压输出; 多个触发器,其耦合到NMOS晶体管的漏极以根据脉冲锁定NMOS晶体管的电压输出; 内部电压产生单元耦合到输入节点以提供浮动电压电平; 以及由用于控制电压选择电路的正常操作的脉冲控制的多个开关以及内部电压产生单元与输入节点之间的导通。

    Pulse width modulation regulator system with automatically switching pulse skipping mode
    22.
    发明申请
    Pulse width modulation regulator system with automatically switching pulse skipping mode 有权
    脉宽调制调节系统具有自动切换脉冲跳跃模式

    公开(公告)号:US20060268974A1

    公开(公告)日:2006-11-30

    申请号:US11272699

    申请日:2005-11-15

    CPC classification number: H02M3/156

    Abstract: A pulse width modulation (PWM) Regulator System with automatically switching pulse skipping mode (PSM) is disclosed. The PWM regulator system comprises a PWM regulator, a PSM switching module and a pulse generator. The PWM regulator converts the input voltage by PWM. The PSM switching module determines to enter or exit the PSM. The pulse generator adaptively produces pulse signal for the switching regulator to operate in PSM.

    Abstract translation: 公开了具有自动切换脉冲跳跃模式(PSM)的脉冲宽度调制(PWM)调节器系统。 PWM调节器系统包括PWM调节器,PSM开关模块和脉冲发生器。 PWM调节器通过PWM转换输入电压。 PSM切换模块确定进入或退出PSM。 脉冲发生器自适应地产生用于开关调节器的脉冲信号以在PSM中操作。

    Method for determining switching state of a transistor-based switching device
    23.
    发明申请
    Method for determining switching state of a transistor-based switching device 有权
    用于确定基于晶体管的开关器件的开关状态的方法

    公开(公告)号:US20060109046A1

    公开(公告)日:2006-05-25

    申请号:US11108742

    申请日:2005-04-19

    CPC classification number: H03K17/0822 H03K3/00 H03K17/00 H03K17/18 H03K17/6871

    Abstract: A method, which is for determining switching state of a transistor-based switching device that includes a set of transistors, includes the steps of: applying a bias voltage to a transistor having a fastest response so as to dispose the transistors in the set in a desired transistor state; detecting a voltage level at a transistor having a slowest response to the bias voltage; and comparing the detected voltage level with a predetermined threshold voltage level in order to determine the switching state of the switching device. A transistor-based switching device is also disclosed.

    Abstract translation: 一种用于确定包括一组晶体管的基于晶体管的开关器件的开关状态的方法包括以下步骤:将偏置电压施加到具有最快响应的晶体管,以将晶体管置于该组中的晶体管中 所需晶体管状态; 检测对所述偏置电压具有最慢响应的晶体管的电压电平; 以及将检测到的电压电平与预定阈值电压电平进行比较,以便确定开关器件的开关状态。 还公开了一种基于晶体管的开关器件。

    LED driver using a depletion mode transistor to serve as a current source
    24.
    发明申请
    LED driver using a depletion mode transistor to serve as a current source 失效
    LED驱动器使用耗尽型晶体管作为电流源

    公开(公告)号:US20050275711A1

    公开(公告)日:2005-12-15

    申请号:US11149292

    申请日:2005-06-10

    CPC classification number: H05B33/0857 H05B33/0818 H05B33/0827 Y02B20/347

    Abstract: In a LED driver using a depletion mode transistor to serve as a current source, the depletion mode transistor is self-biased for providing a driving current to drive at least one LED, thereby requesting no additional control circuit to control the depletion mode transistor. The driving current is independent on the supply voltage coupled to the at least one LED, thereby requesting no additional voltage regulator, reducing the circuit size, and lowering the cost.

    Abstract translation: 在使用耗尽型晶体管作为电流源的LED驱动器中,耗尽型晶体管是自偏置的,用于提供驱动电流以驱动至少一个LED,从而不需要额外的控制电路来控制耗尽型晶体管。 驱动电流独立于耦合到至少一个LED的电源电压,从而不需要额外的电压调节器,减小电路尺寸并降低成本。

    Battery charger
    25.
    发明申请
    Battery charger 审中-公开
    充电器

    公开(公告)号:US20050253558A1

    公开(公告)日:2005-11-17

    申请号:US11122035

    申请日:2005-05-05

    CPC classification number: H02J7/008

    Abstract: A battery charger comprises a power input to be connected to a power supply, a charge node to be connected with a battery, a N-channel or P-channel JFET coupled between the power input and the charge node, and a controller to monitor the voltage of the battery to control the JFET.

    Abstract translation: 电池充电器包括要连接到电源的电源输入,要与电池连接的充电节点,耦合在电力输入和充电节点之间的N沟道或P沟道JFET,以及控制器,用于监视 电池的电压来控制JFET。

    Programmable voltage supervisory circuit and method with minimum programming pins and low quiescent current
    27.
    发明授权
    Programmable voltage supervisory circuit and method with minimum programming pins and low quiescent current 失效
    可编程电压监控电路和方法,具有最小编程引脚和低静态电流

    公开(公告)号:US06844709B2

    公开(公告)日:2005-01-18

    申请号:US10283062

    申请日:2002-10-30

    CPC classification number: G05F1/565

    Abstract: A programmable voltage supervisory circuit and method with minimum programming pins and low quiescent current is provided to monitor a supply voltage, by which only one programming pin can configure three voltage levels for the threshold voltage to be compared to the supply voltage. The programming pin is connected with a voltage select signal that is defined to be high, low or floating states each determines a setting voltage among three levels corresponding to the three threshold voltages, respectively, by a voltage select circuit. A sample/hold circuit in combination with a switch arrangement is further connected to the voltage select circuit such that the programmable voltage supervisory circuit is only operationable during the duty of a clock and thereby to reduce the power consumption thereof by squeezing the duty.

    Abstract translation: 提供了具有最小编程引脚和低静态电流的可编程电压监控电路和方法来监视电源电压,只有一个编程引脚可以配置三个电压电平,以将阈值电压与电源电压进行比较。 编程引脚与被定义为高,低或浮置状态的电压选择信号连接,分别通过电压选择电路确定对应于三个阈值电压的三个电平之间的设定电压。 与开关装置组合的采样/保持电路还与电压选择电路连接,使得可编程电压监控电路仅在时钟的占空比期间可操作,从而通过压缩占空比来减少其功耗。

    Two-step ripple-free multi-phase buck converter and method thereof
    28.
    发明授权
    Two-step ripple-free multi-phase buck converter and method thereof 有权
    两级无波纹多相降压转换器及其方法

    公开(公告)号:US06839252B2

    公开(公告)日:2005-01-04

    申请号:US10442077

    申请日:2003-05-21

    CPC classification number: H02M3/1584 H02M2001/0029

    Abstract: A two-step ripple-free multi-phase buck converter and method thereof comprises a first-stage voltage regulator to convert an input voltage to an intermediate voltage and a second-stage voltage regulator with a phase number not less than two to further convert the intermediate voltage to an output voltage by a split phase control, in which the ratio of the intermediate voltage to the output voltage is intended to the phase number such that the steady state output current of the converter approaches to be ripple-free, and hence the drivers and MOSFETs for the second-stage voltage regulator are lower cost, the efficiency of the second-stage voltage regulator is improved, and a higher slew rate current is obtained for transient driving capabilities.

    Abstract translation: 两级无纹波多相降压转换器及其方法包括将输入电压转换为中间电压的第一级电压调节器和相位数不少于2的第二级稳压器,以进一步转换 通过分相控制将中间电压输出到输出电压,其中中间电压与输出电压的比率旨在达到相位数,使得转换器的稳态输出电流接近无波纹,因此 第二级稳压器的驱动器和MOSFET的成本较低,二级稳压器的效率得到提高,瞬态驱动能力可获得更高的转换速率电流。

    Apparatus and method for balancing channel currents in a multi-phase DC-to-DC converter
    29.
    发明授权
    Apparatus and method for balancing channel currents in a multi-phase DC-to-DC converter 有权
    用于平衡多相DC-DC转换器中的通道电流的装置和方法

    公开(公告)号:US06414470B1

    公开(公告)日:2002-07-02

    申请号:US10051136

    申请日:2002-01-22

    CPC classification number: H02M3/1584 H02J1/102

    Abstract: An apparatus and method for current balance in a multi-phase DC-to-DC converter with a converter output voltage and a plurality of channel currents employs for each channel a multi-input pulse width modulator or an ordinary pulse width modulator in conjunction with a multi-input comparator to produce a respective PWM signal to regulate the corresponding channel current. In addition to the comparison of the converter output voltage with a reference signal to produce an error signal, the apparatus and method compares the error signal with a ramp signal and the corresponding channel current with each of the other channel currents with the multi-input pulse width modulator. Alternatively, a ramp signal is compared by the ordinary pulse width modulator with a signal derived from the multi-input comparator which subtracts the corresponding channel current from each other channel current and sums the error signal.

    Abstract translation: 具有转换器输出电压和多个通道电流的多相DC-DC转换器中的电流平衡的装置和方法为每个通道使用多输入脉宽调制器或普通脉冲宽度调制器 多输入比较器产生相应的PWM信号来调节相应的通道电流。 除了将转换器输出电压与参考信号进行比较以产生误差信号之外,装置和方法还将误差信号与斜波信号和相应的通道电流与多输入脉冲中的每一个通道电流进行比较 宽度调制器 或者,通过普通脉冲宽度调制器将斜坡信号与从多输入比较器导出的信号进行比较,该信号从彼此的通道电流中减去对应的通道电流,并对误差信号求和。

    Place and route method for integrated circuit design
    30.
    发明授权
    Place and route method for integrated circuit design 有权
    集成电路设计的放置和布线方法

    公开(公告)号:US06207479B1

    公开(公告)日:2001-03-27

    申请号:US09332127

    申请日:1999-06-14

    CPC classification number: H01L27/118 H01L23/528 H01L2924/0002 H01L2924/00

    Abstract: The present invention provides a method of placing and routing metal wires for integrated circuit. In the method, a grid pattern is constructed by a plurality of floors with metal wires The grid size is set to be equal to a metal pitch. However, each via placed in the grid pattern has to be constrained by a checkerboard-like pattern. The checkerboard-like pattern consists of potential via sites and forbidden sites, wherein the potential via sites and the forbidden sites are intervened each other so that each potential via site in a comer of the grid has forbidden sites at its nearest neighbor corners. Furthermore, the connection cells is constructed and placed in a defined via site for connecting the metal wires in individually floor.

    Abstract translation: 本发明提供了一种用于集成电路放置和布线金属线的方法。 在该方法中,网格图案由具有金属线的多个楼层构成。网格尺寸被设定为等于金属间距。 然而,放置在网格图案中的每个通道必须受到棋盘样图案的约束。 类似棋盘的模式包括通过站点和禁止站点的潜在可能性,其中通过站点和禁止站点的潜在位置彼此干预,使得网格中的每个潜在通过站点在其最近的相邻角落处禁止站点。 此外,连接单元被构造并放置在限定的通孔位置中,用于将金属线连接在单独的地板中。

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