Abstract:
A voltage generating circuit, which generates tri-state logic output in accordance with high, low or floating of the input node, is proposed. The present voltage generating circuit includes: a pulse generating circuit for generating a plurality of pulses; a voltage selecting circuit having a pair of NMOS transistors coupled in common source, each drain of the NMOS transistors is coupled to a current source respectively, both gates of the NMOS transistors are coupled to an input node, and the paired drain of the NMOS transistors generate a pair of voltage output; a plurality of flip-flops, which couple to drains of the NMOS transistors to lock the voltage output of the NMOS transistors in accordance with the pulses; an inner voltage-generating unit couples to the input node for providing a floating voltage level; and a plurality of switches controlled by the pulses for controlling the normal operation of the voltage selecting circuit and the conduction between the inner-voltage generating unit with the input node.
Abstract:
A pulse width modulation (PWM) Regulator System with automatically switching pulse skipping mode (PSM) is disclosed. The PWM regulator system comprises a PWM regulator, a PSM switching module and a pulse generator. The PWM regulator converts the input voltage by PWM. The PSM switching module determines to enter or exit the PSM. The pulse generator adaptively produces pulse signal for the switching regulator to operate in PSM.
Abstract:
A method, which is for determining switching state of a transistor-based switching device that includes a set of transistors, includes the steps of: applying a bias voltage to a transistor having a fastest response so as to dispose the transistors in the set in a desired transistor state; detecting a voltage level at a transistor having a slowest response to the bias voltage; and comparing the detected voltage level with a predetermined threshold voltage level in order to determine the switching state of the switching device. A transistor-based switching device is also disclosed.
Abstract:
In a LED driver using a depletion mode transistor to serve as a current source, the depletion mode transistor is self-biased for providing a driving current to drive at least one LED, thereby requesting no additional control circuit to control the depletion mode transistor. The driving current is independent on the supply voltage coupled to the at least one LED, thereby requesting no additional voltage regulator, reducing the circuit size, and lowering the cost.
Abstract:
A battery charger comprises a power input to be connected to a power supply, a charge node to be connected with a battery, a N-channel or P-channel JFET coupled between the power input and the charge node, and a controller to monitor the voltage of the battery to control the JFET.
Abstract:
A frame-shifted technique is disclosed for a dynamic gamma correction method and system that comprises counting the gray levels of each frame to figure out the probability distribution of gray levels in the current frame, and determining the gamma reference voltages according to the probability distribution of gray levels of the current frame for the gamma correction of the next frame.
Abstract:
A programmable voltage supervisory circuit and method with minimum programming pins and low quiescent current is provided to monitor a supply voltage, by which only one programming pin can configure three voltage levels for the threshold voltage to be compared to the supply voltage. The programming pin is connected with a voltage select signal that is defined to be high, low or floating states each determines a setting voltage among three levels corresponding to the three threshold voltages, respectively, by a voltage select circuit. A sample/hold circuit in combination with a switch arrangement is further connected to the voltage select circuit such that the programmable voltage supervisory circuit is only operationable during the duty of a clock and thereby to reduce the power consumption thereof by squeezing the duty.
Abstract:
A two-step ripple-free multi-phase buck converter and method thereof comprises a first-stage voltage regulator to convert an input voltage to an intermediate voltage and a second-stage voltage regulator with a phase number not less than two to further convert the intermediate voltage to an output voltage by a split phase control, in which the ratio of the intermediate voltage to the output voltage is intended to the phase number such that the steady state output current of the converter approaches to be ripple-free, and hence the drivers and MOSFETs for the second-stage voltage regulator are lower cost, the efficiency of the second-stage voltage regulator is improved, and a higher slew rate current is obtained for transient driving capabilities.
Abstract:
An apparatus and method for current balance in a multi-phase DC-to-DC converter with a converter output voltage and a plurality of channel currents employs for each channel a multi-input pulse width modulator or an ordinary pulse width modulator in conjunction with a multi-input comparator to produce a respective PWM signal to regulate the corresponding channel current. In addition to the comparison of the converter output voltage with a reference signal to produce an error signal, the apparatus and method compares the error signal with a ramp signal and the corresponding channel current with each of the other channel currents with the multi-input pulse width modulator. Alternatively, a ramp signal is compared by the ordinary pulse width modulator with a signal derived from the multi-input comparator which subtracts the corresponding channel current from each other channel current and sums the error signal.
Abstract:
The present invention provides a method of placing and routing metal wires for integrated circuit. In the method, a grid pattern is constructed by a plurality of floors with metal wires The grid size is set to be equal to a metal pitch. However, each via placed in the grid pattern has to be constrained by a checkerboard-like pattern. The checkerboard-like pattern consists of potential via sites and forbidden sites, wherein the potential via sites and the forbidden sites are intervened each other so that each potential via site in a comer of the grid has forbidden sites at its nearest neighbor corners. Furthermore, the connection cells is constructed and placed in a defined via site for connecting the metal wires in individually floor.