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38 条记录 (耗时 0.025 秒)

    Resistance mirror circuit
    1.
    发明授权
    Resistance mirror circuit 失效
    电阻镜电路

    公开(公告)号：US06747508B2

    公开(公告)日：2004-06-08

    申请号：US10229160

    申请日：2002-08-28

    申请人： Jing-Meng Liu ,  Kent Hwang ,  Chao-Hsuan Chuang ,  Cheng-Hsuan Fan

    发明人： Jing-Meng Liu ,  Kent Hwang ,  Chao-Hsuan Chuang ,  Cheng-Hsuan Fan

    IPC分类号： G05F110

    CPC分类号： G05F3/262

    摘要： A resistance adjustable of resistance mirror circuit having a master resistor R0, a reference current source terminal providing a current value I0 through the master resistor R0 to ground; a first transistor; a current mirror source terminal providing a current value n I0, through the first transistor to ground; an operational amplifier having a positive terminal connecting to a drain of the first transistor, a negative terminal connecting to the other terminal of the master resistor R0, and an output terminal connecting to a gate of the first transistor; a mirror resistor set composed of a plurality of transistors in parallel each other and having their source electrode connecting to ground. Each transistor of the mirror resistor set has a ratio of channel width over channel length being m-fold of that of the first transistor, where m, n is any positive numbers. Since gates of the transistors connect to the output terminal of the operational amplifier, each of the transistors therefore has an equivalent resistance Req=(1/nm)R0.

    摘要翻译： 电阻镜电路的电阻可调，具有主电阻器R0，参考电流源端子通过主电阻器R0接地提供电流值I0; 第一晶体管; 电流镜源端子，通过第一晶体管接地提供电流值n I0; 具有连接到第一晶体管的漏极的正端子的运算放大器，连接到主电阻器R0的另一端子的负极端子和连接到第一晶体管的栅极的输出端子; 由多个彼此并联的晶体管组成并且其源电极连接到地的镜电阻器组。 镜面电阻器组的每个晶体管的沟道宽度与沟道长度的比率与第一晶体管的沟道长度的m倍成正比，其中m，n是任何正数。 由于晶体管的栅极连接到运算放大器的输出端，因此每个晶体管具有等效电阻Req =（1 / nm）R0。

    Programmable voltage supervisory circuit and method with minimum programming pins and low quiescent current
    2.
    发明授权
    Programmable voltage supervisory circuit and method with minimum programming pins and low quiescent current 失效
    可编程电压监控电路和方法，具有最小编程引脚和低静态电流

    公开(公告)号：US06844709B2

    公开(公告)日：2005-01-18

    申请号：US10283062

    申请日：2002-10-30

    申请人： Chao-Hsuan Chuang ,  Jing-Meng Liu ,  Cheng-Hsuan Fan ,  Kent Hwang

    发明人： Chao-Hsuan Chuang ,  Jing-Meng Liu ,  Cheng-Hsuan Fan ,  Kent Hwang

    IPC分类号： G05F1/565 ,  G05F1/40 ,  G05F1/618

    CPC分类号： G05F1/565

    摘要： A programmable voltage supervisory circuit and method with minimum programming pins and low quiescent current is provided to monitor a supply voltage, by which only one programming pin can configure three voltage levels for the threshold voltage to be compared to the supply voltage. The programming pin is connected with a voltage select signal that is defined to be high, low or floating states each determines a setting voltage among three levels corresponding to the three threshold voltages, respectively, by a voltage select circuit. A sample/hold circuit in combination with a switch arrangement is further connected to the voltage select circuit such that the programmable voltage supervisory circuit is only operationable during the duty of a clock and thereby to reduce the power consumption thereof by squeezing the duty.

    摘要翻译： 提供了具有最小编程引脚和低静态电流的可编程电压监控电路和方法来监视电源电压，只有一个编程引脚可以配置三个电压电平，以将阈值电压与电源电压进行比较。 编程引脚与被定义为高，低或浮置状态的电压选择信号连接，分别通过电压选择电路确定对应于三个阈值电压的三个电平之间的设定电压。 与开关装置组合的采样/保持电路还与电压选择电路连接，使得可编程电压监控电路仅在时钟的占空比期间可操作，从而通过压缩占空比来减少其功耗。

    Synchronized data communication on a one-wired bus
    3.
    发明授权
    Synchronized data communication on a one-wired bus 失效
    在单线总线上同步数据通信

    公开(公告)号：US07180886B2

    公开(公告)日：2007-02-20

    申请号：US10153784

    申请日：2002-05-24

    申请人： Jing-Meng Liu ,  Kent Hwang ,  Chao-Hsuan Chuang ,  Cheng-Hsuan Fan

    发明人： Jing-Meng Liu ,  Kent Hwang ,  Chao-Hsuan Chuang ,  Cheng-Hsuan Fan

    IPC分类号： H04J3/06 ,  H04L12/50

    CPC分类号： H04L25/4923 ,  H04L7/06 ,  H04L25/4904

    摘要： In a synchronized data communication on a one-wired bus, it transmits and receives a synchronizing signal that segments part of or all proportions of the data signal by use of three electrically distinguishable statuses for the identifier of the synchronizing signal and the logic states of the data signal to increase the endurance of frequency displacement and resist influences of the interference of external conditions, low quality of transmission medium, and limitation of transmission distance and make the reliability and correctness of the signal transmission improve substantially. It is also clearly illustrated the feasibility and simplicity for implementing the one-wired synchronized communication by a plurality of exemplary signal types and a transceiver circuitry.

    摘要翻译： 在单线总线上的同步数据通信中，它发送和接收同步信号，该同步信号通过使用用于同步信号的标识符的三个电可区分状态以及数据信号的逻辑状态来分割数据信号的一部分或全部比例 数据信号增加频率位移的耐久性，抵抗外部条件干扰，传输介质质量差，传输距离限制的影响，使信号传输的可靠性和正确性大大提高。 还清楚地示出了通过多个示例性信号类型和收发器电路来实现单线同步通信的可行性和简单性。

    Inductor equivalent circuit and application thereof
    4.
    发明授权
    Inductor equivalent circuit and application thereof 失效
    电感等效电路及其应用

    公开(公告)号：US06809616B2

    公开(公告)日：2004-10-26

    申请号：US10342183

    申请日：2003-01-15

    申请人： Jing-Meng Liu ,  Kent Hwang ,  Chao-Hsuan Chuang ,  Cheng-Hsuan Fan

    发明人： Jing-Meng Liu ,  Kent Hwang ,  Chao-Hsuan Chuang ,  Cheng-Hsuan Fan

    IPC分类号： H03H1100

    CPC分类号： H03H11/485 ,  H03H11/48

    摘要： An inductor equivalent circuit is disclosed. The circuit comprises a reference current source, a first current mirror, a second current mirror, two operational amplifiers OP1 and OP2, a capacitor, a first transistor, a second transistor, a mirror resistor set, and a bypass current source in parallel with the capacitor. An input signal is through OP1 and second transistor to control the reference current source. The first mirror current is then feed-back a signal to the first transistor through an OP2. The current signal makes the drain current of the first transistor lags the input voltage signal by 90° due to the capacitor coupled with the first mirror current source. The mirror resistor set can be resistors having one common terminal grounded, and other terminals each, respectively, coupled with the first and the second transistor and the capacitor, or can be composed of transistors and all of them with gate property biased so that the transistors in the mirror resistor set are operated in an ohmic region. The second mirror current provides an output current of the inductor equivalent circuit for next cascade stage.

    摘要翻译： 公开了一种电感器等效电路。 该电路包括参考电流源，第一电流镜，第二电流镜，两个运算放大器OP1和OP2，电容器，第一晶体管，第二晶体管，反射镜电阻器组以及旁路电流源 电容器。 输入信号通过OP1和第二晶体管来控制参考电流源。 然后通过OP2将第一镜电流反馈到第一晶体管。 由于与第一反射镜电流源耦合的电容器，电流信号使得第一晶体管的漏极电流滞留输入电压信号90°。 镜电阻器组可以是具有一个公共端子接地的电阻器，并且其他端子分别与第一和第二晶体管和电容器耦合，或者可以由晶体管组成，并且所有这些端子都具有偏置的栅极特性，使得晶体管 镜面电阻组在欧姆区域工作。 第二镜电流为下一级联级提供电感等效电路的输出电流。

    Load-dependent frequency jittering circuit and load-dependent frequency jittering method
    6.
    发明授权
    Load-dependent frequency jittering circuit and load-dependent frequency jittering method 有权
    负载相关的频率抖动电路和负载相关的频率抖动方法

    公开(公告)号：US07728571B2

    公开(公告)日：2010-06-01

    申请号：US11935558

    申请日：2007-11-06

    申请人： Chao-Hsuan Chuang ,  Cheng-Hsuan Fan ,  Hung-Che Chou ,  Ching-Hsiang Yang

    发明人： Chao-Hsuan Chuang ,  Cheng-Hsuan Fan ,  Hung-Che Chou ,  Ching-Hsiang Yang

    IPC分类号： G05F1/56

    CPC分类号： H03K3/72

    摘要： The present invention discloses a load-dependent frequency jittering circuit, comprising: a load condition detection circuit for receiving a switching signal and generating an output according to a load condition; a number generator for receiving the output of the load condition detection circuit and generating a number; a digital to analog converter for converting the output of the number generator to an analog signal; and an oscillator for generating a jittered frequency according to the output of the digital to analog converter.

    摘要翻译： 本发明公开了一种负载相关的频率抖动电路，包括：负载状态检测电路，用于接收开关信号并根据负载条件产生输出; 数字发生器，用于接收负载状态检测电路的输出并产生一个数字; 用于将数字发生器的输出转换为模拟信号的数模转换器; 以及用于根据数模转换器的输出产生抖动频率的振荡器。

    Arrangement and method for an integrated protection for a power system
    8.
    发明授权
    Arrangement and method for an integrated protection for a power system 有权
    电力系统综合保护的安排和方法

    公开(公告)号：US07535690B2

    公开(公告)日：2009-05-19

    申请号：US11518446

    申请日：2006-09-11

    申请人： Cheng-Hsuan Fan ,  Chao-Hsuan Chuang ,  Hung-Che Chou ,  Ching-Hsiang Yang ,  Chih-Ping Tan

    发明人： Cheng-Hsuan Fan ,  Chao-Hsuan Chuang ,  Hung-Che Chou ,  Ching-Hsiang Yang ,  Chih-Ping Tan

    IPC分类号： H02H3/24 ,  H02H5/04

    CPC分类号： H02H5/041 ,  H02H3/087 ,  H02H3/202

    摘要： For protecting a power system, two or three of over current, thermal and under voltage protection circuits are integrated as one protection circuit but operate independently, and one or more protection points thereof are adjusted dynamically in response to detected condition of the power system. Specifically, using voltage and current conditions in the power system to modify the over current protection and the thermal protection maximizes the performance of the power system and covers the process bias in the circuits.

    摘要翻译： 为了保护电力系统，两个或三个过流，过热和欠压保护电路被集成为一个保护电路，但是独立操作，并且响应于电力系统的检测到的状态来动态地调整其一个或多个保护点。 具体来说，使用电力系统中的电压和电流条件修改过电流保护和热保护，最大限度地提高电力系统的性能，并覆盖电路中的过程偏置。