公开(公告)号：US07688620B2

公开(公告)日：2010-03-30

申请号：US11834843

申请日：2007-08-07

Applicant: Kwang-jin Lee ,  Choong-keun Kwak ,  Du-eung Kim

Inventor： Kwang-jin Lee ,  Choong-keun Kwak ,  Du-eung Kim

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0064

Abstract: In a nonvolatile memory device, a program operation is performed on a plurality of nonvolatile memory cells by programming data having a first logic state in a first group among a plurality of selected memory cells selected from the plurality of nonvolatile memory cells during a first program interval of the program operation, and thereafter, programming data having a second logic state different from the first logic state in a second group among the selected memory cells during a second program interval of the program operation after the first program interval.

Abstract translation: 在非易失性存储器件中，通过在第一程序间隔期间从多个非易失性存储单元中选出的多个选择的存储单元中的第一组中编程具有第一逻辑状态的数据，对多个非易失性存储单元执行编程操作 并且此后，在所述第一编程间隔之后的所述程序操作的第二编程间隔期间，在所选择的存储单元之间具有与所述第二组中的第一逻辑状态不同的第二逻辑状态的编程数据。

公开(公告)号：US20090285008A1

公开(公告)日：2009-11-19

申请号：US12419934

申请日：2009-04-07

Applicant: Hong-Sik Jeong ,  Kwang-Jin Lee ,  Dae-Won Ha ,  Gi-Tae Jeong ,  Jung-Hyuk Lee

Inventor： Hong-Sik Jeong ,  Kwang-Jin Lee ,  Dae-Won Ha ,  Gi-Tae Jeong ,  Jung-Hyuk Lee

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C8/10 ,  G11C7/1006 ,  G11C13/0004 ,  G11C13/0035 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/3459 ,  G11C2013/0076

Abstract: A number of read cycles applied to a selected memory location of a memory device, such as a variable-resistance memory device, is monitored. Write data to be written to the selected memory location is received. Selective pre-write verifying and writing of the received write data to the selected memory location occurs based on the monitored number of read cycles. Selectively pre-write verifying and writing of the received write data may include, for example, writing received write data to the selected memory cell region without pre-write verification responsive to the monitored number of read cycles being greater than a predetermined number of read cycles

Abstract translation: 监视应用于诸如可变电阻存储器件的存储器件的选定存储器位置的多个读周期。 接收要写入所选存储单元的写入数据。 基于所监视的读取周期数，对接收的写入数据进行选择性的预写入验证和写入。 选择性地预写入验证和写入所接收的写入数据可以包括例如将接收到的写入数据写入所选择的存储器单元区域，而无需预写入验证，响应于所监视的读取周期数大于预定数量的读取周期

公开(公告)号：US20080197071A1

公开(公告)日：2008-08-21

申请号：US12063078

申请日：2006-08-08

Applicant: Moo Seok Lee ,  Kwang Jin Lee

Inventor： Moo Seok Lee ,  Kwang Jin Lee

IPC: B01D71/56 ,  B29C47/06

CPC classification number: B01D61/027 ,  B01D69/02 ,  B01D69/085 ,  B01D69/087 ,  B01D69/12 ,  B01D71/56 ,  B01D2325/24 ,  B01D2325/40

Abstract: Disclosed are a nanofiltration composite hollow fiber membrane and a method of manufacturing the same. The nanofiltration composite hollow fiber membrane includes a reinforcement (1) which is a tubular braid, a polymeric resin thin film (2) coated on the outer surface of the reinforcement (1), and a polyamide active layer (3) formed on the outer surface of the polymeric resin thin film. The present invention has an advantage of an excellent strength and an increase in membrane area relative to an installation area.

Abstract translation: 公开了一种纳滤复合中空纤维膜及其制造方法。 纳滤复合中空纤维膜包括：管状编织物的加强件（1），涂覆在加强件（1）的外表面上的聚合物树脂薄膜（2）和形成在外部的聚酰胺活性层（3） 聚合物树脂薄膜的表面。 本发明具有相对于安装面积优异的强度和膜面积的增加的优点。

公开(公告)号：US20080101131A1

公开(公告)日：2008-05-01

申请号：US11790146

申请日：2007-04-24

Applicant: Kwang-Jin Lee ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Woo-Yeong Cho

Inventor： Kwang-Jin Lee ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Woo-Yeong Cho

IPC: G11C7/06

CPC classification number: G11C13/0069 ,  G11C7/06 ,  G11C7/1006 ,  G11C13/0004 ,  G11C2013/0076 ,  G11C2211/5647

Abstract: Embodiments of the invention provide devices or methods that include a status bit representing an inversion of stored data. New data is written to selected cells, the new data is selectively inverted, and the status bit is selectively toggled, based on a comparison between pre-existing data and new data associated with a write command. A benefit of embodiments of the invention is that fewer memory cells must be activated in many instances (when compared to conventional art approaches). Moreover, embodiments of the invention may also reduce the average amount of activation current required to write to variable resistive memory devices and other memory device types.

Abstract translation: 本发明的实施例提供了包括表示存储数据的反转的状态位的设备或方法。 将新数据写入所选择的单元，根据预先存在的数据与与写命令相关联的新数据之间的比较，选择性地反转新数据并选择性地切换状态位。 本发明的实施例的优点在于，在许多情况下（与传统技术方法相比），必须激活更少的存储器单元。 此外，本发明的实施例还可以减少写入可变电阻存储器件和其他存储器件类型所需的平均激活电流量。

公开(公告)号：US20080068872A1

公开(公告)日：2008-03-20

申请号：US11892851

申请日：2007-08-28

Applicant: Kwang-Jin LEE ,  Du-eung KIM

Inventor： Kwang-Jin LEE ,  Du-eung KIM

IPC: G11C15/00

CPC classification number: G11C15/046 ,  G11C13/0004

Abstract: According to an example embodiment, a CAM cell included in a CAM may include a phase change memory device, a connector, and/or a developer. The phase change memory device may be configured to store data. The phase change memory device may have a resistance that may be varied according to the logic level of the stored data. The connector may be configured to control writing data to the phase change memory device and reading data from the phase change memory device. The developer may be configured to control reading data from the phase change memory device in a search mode in which the data stored in the phase change memory device is compared to the search data.

Abstract translation: 根据示例实施例，CAM中包括的CAM单元可以包括相变存储器件，连接器和/或显影器。 相变存储器件可以被配置为存储数据。 相变存储器件可以具有可以根据存储的数据的逻辑电平而改变的电阻。 连接器可以被配置为控制向相变存储器件写入数据并从相变存储器件读取数据。 开发者可以被配置为在存储在相变存储器件中的数据与搜索数据进行比较的搜索模式中控制从相变存储器件读取数据。

公开(公告)号：US07283387B2

公开(公告)日：2007-10-16

申请号：US11316256

申请日：2005-12-23

Applicant: Woo-yeong Cho ,  Du-eung Kim ,  Kwang-jin Lee ,  Choong-keun Kwak

Inventor： Woo-yeong Cho ,  Du-eung Kim ,  Kwang-jin Lee ,  Choong-keun Kwak

IPC: G11C11/00 ,  G11C5/14

CPC classification number: G11C13/0038 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/72

Abstract: A phase change memory device includes a memory array including a plurality of phase change memory cells, each phase change memory cell including a phase change material and a diode, a plurality of column selection transistors connecting bit lines connected to the phase change memory cells to corresponding data lines, and a control node connecting the data lines to a sense amplifier unit. In a write operation mode, control voltages obtained by boosting a first voltage are respectively applied to the control node and gates of the column selection transistors, and a ground voltage is applied to a word line of a selected one of the phase change memory cells. In a standby mode, word lines and bit lines connected to the phase change memory cells of the memory array are maintained at the same voltage. According to the phase change memory device and a driving method thereof, a sufficient write voltage is supplied to a write driver, a column decoder and a row decoder in the write operation mode, and a voltage lower is applied to the write driver, the column decoder and the row decoder in the read operation mode and the standby mode, thereby reducing current consumption and enhancing operational reliability.

Abstract translation: 相变存储器件包括包括多个相变存储器单元的存储器阵列，每个相变存储单元包括相变材料和二极管，多个列选择晶体管将连接到相变存储单元的位线连接到相应的 数据线和将数据线连接到读出放大器单元的控制节点。 在写入操作模式中，通过升压第一电压获得的控制电压分别施加到列选择晶体管的控制节点和栅极，并且将接地电压施加到所选择的一个相变存储单元的字线。 在备用模式中，连接到存储器阵列的相变存储单元的字线和位线保持在相同的电压。 根据相变存储器件及其驱动方法，在写入操作模式中向写入驱动器，列解码器和行解码器提供足够的写入电压，并且将较低的电压施加到写入驱动器，列 解码器和行解码器处于读取操作模式和待机模式，从而降低电流消耗并提高操作可靠性。

公开(公告)号：US20070064473A1

公开(公告)日：2007-03-22

申请号：US11319373

申请日：2005-12-29

Applicant: Kwang-Jin Lee ,  Du-Eung Kim ,  Sang-Beom Kang ,  Woo-Yeong Cho

Inventor： Kwang-Jin Lee ,  Du-Eung Kim ,  Sang-Beom Kang ,  Woo-Yeong Cho

IPC: G11C11/00

CPC classification number: G11C5/145 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/79

Abstract: A phase change memory device includes a memory cell having a phase change material, a write driver adapted to supply a program current to the memory cell during a programming interval, and a pump circuit adapted to enhance a current supply capacity of the write driver during the programming interval. The pump circuit is activated prior to the programming interval in response to an external control signal.

Abstract translation: 相变存储器件包括具有相变材料的存储单元，适于在编程间隔期间向存储单元提供编程电流的写入驱动器，以及用于在写入驱动器期间增强写入驱动器的电流供应容量的泵电路 编程间隔。 泵电路响应于外部控制信号在编程间隔之前被激活。

公开(公告)号：US20070058425A1

公开(公告)日：2007-03-15

申请号：US11316256

申请日：2005-12-23

Applicant: Woo-yeong Cho ,  Du-eung Kim ,  Kwang-jin Lee ,  Choong-keun Kwak

Inventor： Woo-yeong Cho ,  Du-eung Kim ,  Kwang-jin Lee ,  Choong-keun Kwak

IPC: G11C11/00

CPC classification number: G11C13/0038 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/72

Abstract: A phase change memory device includes a memory array including a plurality of phase change memory cells, each phase change memory cell including a phase change material and a diode, a plurality of column selection transistors connecting bit lines connected to the phase change memory cells to corresponding data lines, and a control node connecting the data lines to a sense amplifier unit. In a write operation mode, control voltages obtained by boosting a first voltage are respectively applied to the control node and gates of the column selection transistors, and a ground voltage is applied to a word line of a selected one of the phase change memory cells. In a standby mode, word lines and bit lines connected to the phase change memory cells of the memory array are maintained at the same voltage. According to the phase change memory device and a driving method thereof, a sufficient write voltage is supplied to a write driver, a column decoder and a row decoder in the write operation mode, and a voltage lower is applied to the write driver, the column decoder and the row decoder in the read operation mode and the standby mode, thereby reducing current consumption and enhancing operational reliability.

公开(公告)号：US20060291277A1

公开(公告)日：2006-12-28

申请号：US11315347

申请日：2005-12-23

Applicant: Beak-hyung Cho ,  Kwang-jin Lee ,  Mu-hui Park

Inventor： Beak-hyung Cho ,  Kwang-jin Lee ,  Mu-hui Park

IPC: G11C11/00

CPC classification number: G11C11/5678 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0028 ,  G11C2213/72

Abstract: A phase change memory device has a word line driver layout which allows for a reduction in the size a core area of the device. In one aspect, phase change memory device includes a plurality of memory cell blocks sharing a word line, and a plurality of word line drivers driving the word line. Each of the word line drivers includes a precharge device for precharging the word line and a discharge device for discharging the word line, and where the precharge device and the discharge device are alternately located between the plurality of memory cell blocks.

公开(公告)号：US06785173B2

公开(公告)日：2004-08-31

申请号：US10352163

申请日：2003-01-28

Applicant: Kwon-Il Sohn ,  Uk-Rae Cho ,  Kwang-Jin Lee

Inventor： Kwon-Il Sohn ,  Uk-Rae Cho ,  Kwang-Jin Lee

IPC: G11C2900

CPC classification number: G11C29/12015 ,  G11C29/14

Abstract: A semiconductor memory device generates a test clock signal (whose periods and cycle number are variable) having a shorter cycle than that of an external clock signal, and internally test data using the test clock signal. The semiconductor memory device may repeatedly perform read/write operations using the internally generated test clock signal during a half cycle of the external clock signal. By comparing output data in the read operation with known data, a test apparatus may determine whether memory cells of a memory device are normal. In a low-frequency test apparatus, it is possible to screen disadvantages that may occur when a high-speed memory device operates at a high frequency.

Abstract translation: 半导体存储器件产生具有比外部时钟信号更短周期的测试时钟信号（其周期和周期数可变），并且使用测试时钟信号内部测试数据。 半导体存储器件可以在外部时钟信号的半周期期间使用内部产生的测试时钟信号重复执行读/写操作。 通过将读取操作中的输出数据与已知数据进行比较，测试装置可以确定存储器件的存储器单元是否正常。 在低频测试装置中，可以屏蔽当高速存储器件以高频工作时可能发生的缺点。