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56 条记录 (耗时 0.019 秒)

    Method for fabricating strained-silicon CMOS transistors
    21.
    发明授权
    Method for fabricating strained-silicon CMOS transistors 有权
    制造应变硅CMOS晶体管的方法

    公开(公告)号：US07618856B2

    公开(公告)日：2009-11-17

    申请号：US11566688

    申请日：2006-12-05

    申请人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Jing-Chang Wu ,  Kun-Hsien Lee ,  Wen-Han Hung ,  Li-Shian Jeng ,  Tzer-Min Shen ,  Tzyy-Ming Cheng ,  Nien-Chung Li

    发明人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Jing-Chang Wu ,  Kun-Hsien Lee ,  Wen-Han Hung ,  Li-Shian Jeng ,  Tzer-Min Shen ,  Tzyy-Ming Cheng ,  Nien-Chung Li

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L21/823835 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843

    摘要： A semiconductor substrate having a first active region and a second active region for fabricating a first transistor and a second transistor is provided. A first gate structure and a second gate structure are formed on the first active region and the second active region and a first spacer is formed surrounding the first gate structure and the second gate structure. A source/drain region for the first transistor and the second transistor is formed. The first spacer is removed from the first gate structure and the second gate structure and a cap layer is disposed on the first transistor and the second transistor and the cap layer covering the second transistor is removed thereafter. An etching process is performed to form a recess in the substrate surrounding the second gate structure. An epitaxial layer is formed in the recess and the cap layer is removed from the first transistor.

    摘要翻译： 提供具有用于制造第一晶体管和第二晶体管的第一有源区和第二有源区的半导体衬底。 在第一有源区和第二有源区上形成第一栅极结构和第二栅极结构，并且围绕第一栅极结构和第二栅极结构形成第一间隔物。 形成第一晶体管和第二晶体管的源极/漏极区域。 第一间隔物从第一栅极结构和第二栅极结构去除，并且帽层设置在第一晶体管上，并且其后去除第二晶体管和覆盖第二晶体管的覆盖层。 执行蚀刻工艺以在围绕第二栅极结构的基板中形成凹部。 在凹部中形成外延层，并且从第一晶体管去除覆盖层。

    COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR TRANSISTOR AND METHOD OF FABRICATING THE SAME
    26.
    发明申请
    COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR TRANSISTOR AND METHOD OF FABRICATING THE SAME 审中-公开
    补充金属氧化物半导体晶体管及其制造方法

    公开(公告)号：US20080237734A1

    公开(公告)日：2008-10-02

    申请号：US11693470

    申请日：2007-03-29

    申请人： Wen-Han Hung ,  Cheng-Tung Huang ,  Kun-Hsien Lee ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Meng-Yi Wu ,  Chung-Min Shih ,  Tzyy-Ming Cheng ,  Chia-Wen Liang

    发明人： Wen-Han Hung ,  Cheng-Tung Huang ,  Kun-Hsien Lee ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Meng-Yi Wu ,  Chung-Min Shih ,  Tzyy-Ming Cheng ,  Chia-Wen Liang

    IPC分类号： H01L29/76 ,  H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

    摘要： A complementary metal-oxide-semiconductor (CMOS) transistor comprising a substrate, a first conductive type MOS transistor, a second conductive type MOS transistor, a buffer layer, a first stress layer and a second stress layer is provided. The substrate has a device isolation structure therein that defines a first active area and a second active area. The first conductive type MOS transistor and the second conductive type MOS transistor are respectively disposed in the first active area and the second active area of the substrate. A first nitride spacer of the first conductive type MOS transistor has a thickness greater than that of a second nitride spacer of the second conductive type MOS transistor. The buffer layer is disposed on the first conductive type MOS transistor. The first stress layer is disposed on the buffer layer. The second stress layer is disposed on the second conductive type MOS transistor.

    摘要翻译： 提供了包括基板，第一导电型MOS晶体管，第二导电型MOS晶体管，缓冲层，第一应力层和第二应力层的互补金属氧化物半导体（CMOS）晶体管。 衬底在其中具有限定第一有源区和第二有源区的器件隔离结构。 第一导电型MOS晶体管和第二导电型MOS晶体管分别设置在基板的第一有源区域和第二有源区域中。 第一导电型MOS晶体管的第一氮化物间隔物的厚度大于第二导电型MOS晶体管的第二氮化物间隔物的厚度。 缓冲层设置在第一导电型MOS晶体管上。 第一应力层设置在缓冲层上。 第二应力层设置在第二导电型MOS晶体管上。

    SEMICONDUCTOR DEVICE
    30.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20110156156A1

    公开(公告)日：2011-06-30

    申请号：US13044322

    申请日：2011-03-09

    申请人： Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Tzyy-Ming Cheng ,  Chia-Wen Liang

    发明人： Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Tzyy-Ming Cheng ,  Chia-Wen Liang

    IPC分类号： H01L27/092

    CPC分类号： H01L21/823412 ,  H01L21/823468 ,  H01L29/7842

    摘要： A semiconductor device comprises a substrate, a first stress, and a second stress. The substrate has a first-type MOS transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor formed thereon. The first-type and the second-type are opposite conductivity types with respect to each other. The first stress layer is only disposed on the first-type MOS transistor, and the second stress layer is different from the first stress, and is only disposed on the core second-type MOS transistor. The I/O second-type MOS transistor is a type of I/O MOS transistor and without not noly the first stress layer but also the second stress layer disposed thereon, the core second-type MOS transistor is a type of core MOS transistor.

    摘要翻译： 半导体器件包括衬底，第一应力和第二应力。 该基板具有形成在其上的第一型MOS晶体管，输入/输出（I / O）第二型MOS晶体管和核心第二型MOS晶体管。 第一类和第二类是相对于彼此相反的导电类型。 第一应力层仅设置在第一型MOS晶体管上，第二应力层与第一应力不同，并且仅设置在芯型二次型MOS晶体管上。 I / O第二型MOS晶体管是一种I / O MOS晶体管，并不是第一应力层，也是第二应力层，其中核心第二型MOS晶体管是一种核心MOS晶体管。