公开(公告)号：US07505356B2

公开(公告)日：2009-03-17

申请号：US11853708

申请日：2007-09-11

申请人： Frederick A. Ware ,  Lawrence Lai ,  Chad A. Bellows ,  Wayne S. Richardson

发明人： Frederick A. Ware ,  Lawrence Lai ,  Chad A. Bellows ,  Wayne S. Richardson

IPC分类号： G11C8/14

CPC分类号： G11C8/10 ,  G11C8/12 ,  G11C8/16

摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.

摘要翻译： 存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。 集成电路存储器件包括一个接口和列解码器，以访问一行存储单元或存储体中的一页。 在第一操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。 在第二操作模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。 响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。 第一和第二多个存储单元可以从该接口同时访问。

公开(公告)号：US20080279032A1

公开(公告)日：2008-11-13

申请号：US12177357

申请日：2008-07-22

申请人： Kishore Kasamsetty ,  Lawrence Lai ,  Wayne Richardson

发明人： Kishore Kasamsetty ,  Lawrence Lai ,  Wayne Richardson

IPC分类号： G11C8/10

CPC分类号： G11C7/1018 ,  G11C7/1039 ,  G11C7/1048

摘要： An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal.

摘要翻译： 集成电路存储器件，系统和方法实施例以第一时钟频率解码在互连上传送的交错的行和列请求分组。 独立的行解码逻辑和列解码逻辑以相对较慢的第二时钟频率计时，响应于请求数据包中的存储器命令，将独立的列和行控制内部信号输出到存储器内核。 集成电路存储器件包括具有单独的行和列解码逻辑电路的接口，用于提供独立的行和控制信号组。 行解码逻辑电路包括提供诸如行地址的第一行控制信号的第一行解码逻辑电路和提供第二行控制信号的第二行解码逻辑电路。 列解码逻辑电路包括提供诸如列地址的第一列控制信号的第一列解码逻辑电路和提供第二列控制信号的第二列逻辑电路。

公开(公告)号：US07420874B2

公开(公告)日：2008-09-02

申请号：US11099947

申请日：2005-04-06

申请人： Kishore Kasamsetty ,  Lawrence Lai ,  Wayne Richardson

发明人： Kishore Kasamsetty ,  Lawrence Lai ,  Wayne Richardson

IPC分类号： G11C8/18

CPC分类号： G11C7/1018 ,  G11C7/1039 ,  G11C7/1048

摘要： An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal.

摘要翻译： 集成电路存储器件，系统和方法实施例以第一时钟频率解码在互连上传送的交错的行和列请求分组。 独立的行解码逻辑和列解码逻辑以相对较慢的第二时钟频率计时，响应于请求数据包中的存储器命令，将独立的列和行控制内部信号输出到存储器内核。 集成电路存储器件包括具有单独的行和列解码逻辑电路的接口，用于提供独立的行和控制信号组。 行解码逻辑电路包括提供诸如行地址的第一行控制信号的第一行解码逻辑电路和提供第二行控制信号的第二行解码逻辑电路。 列解码逻辑电路包括提供诸如列地址的第一列控制信号的第一列解码逻辑电路和提供第二列控制信号的第二列逻辑电路。

公开(公告)号：US20060227646A1

公开(公告)日：2006-10-12

申请号：US11099947

申请日：2005-04-06

申请人： Kishore Kasamsetty ,  Lawrence Lai ,  Wayne Richardson

发明人： Kishore Kasamsetty ,  Lawrence Lai ,  Wayne Richardson

IPC分类号： G11C8/00

CPC分类号： G11C7/1018 ,  G11C7/1039 ,  G11C7/1048

摘要： An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device comprises an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal.

摘要翻译： 集成电路存储器件，系统和方法实施例以第一时钟频率解码在互连上传送的交错的行和列请求分组。 独立的行解码逻辑和列解码逻辑以相对较慢的第二时钟频率计时，响应于请求数据包中的存储器命令，将独立的列和行控制内部信号输出到存储器内核。 集成电路存储器件包括具有单独的行和列解码逻辑电路的接口，用于提供独立的行和控制信号集合。 行解码逻辑电路包括提供诸如行地址的第一行控制信号的第一行解码逻辑电路和提供第二行控制信号的第二行解码逻辑电路。 列解码逻辑电路包括提供诸如列地址的第一列控制信号的第一列解码逻辑电路和提供第二列控制信号的第二列逻辑电路。

公开(公告)号：US20060117155A1

公开(公告)日：2006-06-01

申请号：US10998402

申请日：2004-11-29

申请人： Frederick Ware ,  Craig Hampel ,  Wayne Richardson ,  Chad Bellows ,  Lawrence Lai

发明人： Frederick Ware ,  Craig Hampel ,  Wayne Richardson ,  Chad Bellows ,  Lawrence Lai

IPC分类号： G06F12/14

CPC分类号： G06F3/0659 ,  G06F3/0613 ,  G06F3/0673 ,  G11C7/1006 ,  G11C7/1042 ,  G11C7/22 ,  G11C8/06 ,  G11C11/4076 ,  G11C11/4097

摘要： A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.

公开(公告)号：US20060072366A1

公开(公告)日：2006-04-06

申请号：US10955193

申请日：2004-09-30

申请人： Frederick Ware ,  Lawrence Lai ,  Chad Bellows ,  Wayne Richardson

发明人： Frederick Ware ,  Lawrence Lai ,  Chad Bellows ,  Wayne Richardson

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C8/12 ,  G11C8/16

摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. During a third mode of operation, a first plurality of storage cells in a first row of storage cells in a first memory bank is accessible in response to a first column address. A second plurality of storage cells in a second row of storage cells in a second bank is accessible in response to a second column address. A third plurality of storage cells in the first row of storage cells is accessible in response to a third column address and a fourth plurality of storage cells in the second row of storage cells is accessible in response to a fourth column address. The first and second column addresses are in a first request packet and the third and fourth column addresses are in a second request packet provided by the master device.

摘要翻译： 存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。 集成电路存储器件包括一个接口和列解码器，以访问一行存储单元或存储体中的一页。 在第一操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。 在第二操作模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。 响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。 在第三操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元中的第一多个存储单元。 响应于第二列地址，可访问第二存储体中第二行存储单元中的第二多个存储单元。 第一行存储单元中的第三多个存储单元响应于第三列地址而可访问，并且第二行存储单元中的第四多个存储单元响应于第四列地址而可访问。 第一列地址和第二列地址在第一请求分组中，并且第三和第四列地址在由主设备提供的第二请求分组中。

公开(公告)号：USRE37409E1

公开(公告)日：2001-10-16

申请号：US09559836

申请日：2000-04-26

申请人： Richard M. Barth ,  Donald C. Stark ,  Lawrence Lai ,  Wayne S. Richardson

发明人： Richard M. Barth ,  Donald C. Stark ,  Lawrence Lai ,  Wayne S. Richardson

IPC分类号： G11C1300

CPC分类号： G11C7/06 ,  G11C8/14 ,  G11C11/4085 ,  G11C11/4091

摘要： A memory and method of operation is disclosed. In one embodiment, the memory includes a group of memory cells divided into a plurality of subgroups. Sub word-lines are selectively coupled to main word lines, each sub-word line corresponding to a subgroup and is coupled to the memory cells in the row of the corresponding subgroup. Sense amplifier circuitry is coupled to the group of memory cells. The sense amplifier circuitry is divided into a plurality of sub-sensing circuits, each of the plurality of sub-sensing circuits selectively coupled to a corresponding one of the plurality of sub-groups. The memory includes a control mechanism to control the word lines and sub-sensing circuit (s) that are activated at any one time such that only those sub-word lines and sub-sensing circuits needed to perform memory operations are operated and consume power. In an alternate embodiment, the control mechanism controls the sub-word lines and sub-sensing circuits to enable substantially concurrent access to different sub-groups of memory cells from different rows of the memory.

摘要翻译： 公开了一种存储器和操作方法。 在一个实施例中，存储器包括分成多个子组的一组存储器单元。 子字线选择性地耦合到主字线，每个子字线对应于一个子组，并且被耦合到相应子组的行中的存储器单元。 感测放大器电路耦合到该组存储器单元。 感测放大器电路被分成多个子感测电路，多个子感测电路中的每一个选择性地耦合到多个子组中对应的一个子组。 存储器包括一个控制机构，用于控制在任何一个时间被激活的字线和子感应电路，使得只需要执行存储器操作所需的子字线和子感测电路并消耗功率。 在替代实施例中，控制机构控制子字线和子感测电路以使得能够从存储器的不同行实质上并发地访问存储器单元的不同子组。

公开(公告)号：US08190808B2

公开(公告)日：2012-05-29

申请号：US10920508

申请日：2004-08-17

申请人： Lawrence Lai ,  Wayne S. Richardson ,  Chad A. Bellows

发明人： Lawrence Lai ,  Wayne S. Richardson ,  Chad A. Bellows

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G11C7/1042 ,  G11C7/22 ,  G11C8/12 ,  G11C2207/2227

摘要： A memory system includes logical banks divided into sub-banks or collections of sub-banks. The memory system responds to memory-access requests (e.g., read and write) directed to a given logical bank by sequentially accessing sub-banks or collections of sub-banks. Sequential access reduces the impact of power-supply spikes induced by memory operations, and thus facilitates improved system performance. Some embodiments of the memory system combine sequential sub-bank access with other performance-enhancing features, such as wider power buses or increased bypass capacitance, to further enhance performance.

摘要翻译： 记忆系统包括分为子银行或子银行集合的逻辑银行。 存储器系统通过顺序地访问子银行或子银行集合来响应指向给定逻辑银行的存储器访问请求（例如，读取和写入）。 顺序访问减少了由存储器操作引起的电源尖峰的影响，从而有助于提高系统性能。 存储器系统的一些实施例将顺序的子银行访问与诸如更宽的电源总线或增加的旁路电容的其他性能增强特征相结合，以进一步提高性能。

公开(公告)号：US20110153932A1

公开(公告)日：2011-06-23

申请号：US13019785

申请日：2011-02-02

申请人： Frederick A. Ware ,  Lawrence Lai ,  Chad A. Bellows ,  Wayne S. Richardson

发明人： Frederick A. Ware ,  Lawrence Lai ,  Chad A. Bellows ,  Wayne S. Richardson

IPC分类号： G06F12/00

CPC分类号： G11C8/10 ,  G11C8/12 ,  G11C8/16

摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.

摘要翻译： 存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。 集成电路存储器件包括一个接口和列解码器，以访问一行存储单元或存储体中的一页。 在第一操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。 在第二操作模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。 响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。 第一和第二多个存储单元可以从该接口同时访问。

公开(公告)号：US07280428B2

公开(公告)日：2007-10-09

申请号：US10955193

申请日：2004-09-30

申请人： Frederick A. Ware ,  Lawrence Lai ,  Chad A. Bellows ,  Wayne S. Richardson

发明人： Frederick A. Ware ,  Lawrence Lai ,  Chad A. Bellows ,  Wayne S. Richardson

IPC分类号： G11C8/14

CPC分类号： G11C8/10 ,  G11C8/12 ,  G11C8/16

摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. During a third mode of operation, a first plurality of storage cells in a first row of storage cells in a first memory bank is accessible in response to a first column address. A second plurality of storage cells in a second row of storage cells in a second bank is accessible in response to a second column address. A third plurality of storage cells in the first row of storage cells is accessible in response to a third column address and a fourth plurality of storage cells in the second row of storage cells is accessible in response to a fourth column address. The first and second column addresses are in a first request packet and the third and fourth column addresses are in a second request packet provided by the master device.

摘要翻译： 存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。 集成电路存储器件包括一个接口和列解码器，以访问一行存储单元或存储体中的一页。 在第一操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。 在第二操作模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。 响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。 在第三操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元中的第一多个存储单元。 响应于第二列地址，可访问第二存储体中第二行存储单元中的第二多个存储单元。 第一行存储单元中的第三多个存储单元响应于第三列地址而可访问，并且第二行存储单元中的第四多个存储单元响应于第四列地址而可访问。 第一列地址和第二列地址在第一请求分组中，并且第三和第四列地址在由主设备提供的第二请求分组中。