利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

89 条记录 (耗时 0.038 秒)

    Methods and circuits for dynamically scaling DRAM power and performance
    1.
    发明授权
    Methods and circuits for dynamically scaling DRAM power and performance 有权
    动态缩放DRAM功率和性能的方法和电路

    公开(公告)号：US08811095B2

    公开(公告)日：2014-08-19

    申请号：US13578864

    申请日：2010-12-01

    申请人： Ely Tsern ,  Thomas Vogelsang ,  Craig Hampel ,  Scott C. Best

    发明人： Ely Tsern ,  Thomas Vogelsang ,  Craig Hampel ,  Scott C. Best

    IPC分类号： G11C7/00

    CPC分类号： G06F3/0625 ,  G06F1/266 ,  G06F3/0634 ,  G06F3/0673 ,  G11C5/147 ,  G11C11/4074 ,  G11C2207/2227

    摘要： A memory system supports high-performance and low-power modes. The memory system includes a memory core and a core interface. The memory core employs core supply voltages that remain the same in both modes. Supply voltages and signaling rates for the core interface may be scaled down to save power. Level shifters between the memory core and core interface level shift signals as needed to accommodate the signaling voltages used by the core interface in the different modes.

    摘要翻译： 内存系统支持高性能和低功耗模式。 存储器系统包括存储器核和核心接口。 存储器内核采用在两种模式下保持相同的核心电源电压。 核心接口的电源电压和信号速率可以缩小以节省功耗。 存储器核心和核心接口电平之间的电平移位器根据需要移位信号以适应不同模式下核心接口所使用的信令电压。

    Signaling system with adaptive timing calibration
    7.
    发明申请
    Signaling system with adaptive timing calibration 有权
    具有自适应定时校准的信号系统

    公开(公告)号：US20070217559A1

    公开(公告)日：2007-09-20

    申请号：US11384148

    申请日：2006-03-16

    申请人： Bret Stott ,  Craig Hampel ,  Frederick Ware

    发明人： Bret Stott ,  Craig Hampel ,  Frederick Ware

    IPC分类号： H04L7/00

    CPC分类号： H04L7/0337 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/20 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2254 ,  H03L7/0814 ,  H04L1/203 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0041

    摘要： An integrated circuit device includes a delay circuit, sampling circuit and delay control circuit that cooperate to carry out adaptive timing calibration. The delay circuit generates a timing signal by delaying an aperiodic input signal for a first interval. The sampling circuit samples a data signal in response to the timing signal to generate a sequence of data samples, and also samples the data signal in response to a phase-shifted version of the timing signal to generate a sequence of edge samples. The delay control circuit adjusts the first interval based, at least in part, on a phase error indicated by the sequence of data samples and the sequence of edge samples.

    摘要翻译： 集成电路装置包括延迟电路，采样电路和延迟控制电路，其协调进行自适应定时校准。 延迟电路通过延迟第一间隔的非周期性输入信号来产生定时信号。 采样电路响应于定时信号对数据信号进行采样以产生数据样本序列，并且还响应于定时信号的相移版本采样数据信号以产生一系列边缘样本。 延迟控制电路至少部分地基于由数据样本序列和边缘样本序列指示的相位误差来调整第一间隔。

    Memory System Having Delayed Write Timing
    8.
    发明申请
    Memory System Having Delayed Write Timing 有权
    具有延迟写入时序的存储器系统

    公开(公告)号：US20070198868A1

    公开(公告)日：2007-08-23

    申请号：US11692162

    申请日：2007-03-27

    申请人： Richard Barth ,  Frederick Ware ,  Donald Stark ,  Craig Hampel ,  Paul Davis ,  Abhijit Abhyankar ,  James Gasbarro ,  David Nguyen

    发明人： Richard Barth ,  Frederick Ware ,  Donald Stark ,  Craig Hampel ,  Paul Davis ,  Abhijit Abhyankar ,  James Gasbarro ,  David Nguyen

    IPC分类号： H04L7/033

    CPC分类号： G11C7/22 ,  G11C7/1006 ,  G11C7/12 ,  G11C8/12 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2218

    摘要： A memory system has first, second and third interconnects and an integrated circuit memory device coupled to the interconnects. The second interconnect conveys a write command and a read command. The third interconnect conveys write data and read data. The integrated circuit memory device includes a pin coupled to the first interconnect to receive a clock signal. The memory device also includes a first plurality of pins coupled to the second interconnect to receive the write command and read command, and a second plurality of pins coupled to the third interconnect to receive write data and to assert read data. Control information is applied to initiate the write operation after a first predetermined delay time transpires from when the write command is received. During a clock cycle of the clock signal, two bits of read data are conveyed by each pin of the second plurality of pins.

    摘要翻译： 存储器系统具有第一，第二和第三互连以及耦合到互连的集成电路存储器件。 第二个互连传送写入命令和读取命令。 第三个互连传送写入数据和读取数据。 集成电路存储器件包括耦合到第一互连的引脚以接收时钟信号。 存储器件还包括耦合到第二互连以接收写入命令和读取命令的第一多个引脚，以及耦合到第三互连以接收写入数据和断言读取数据的第二多个引脚。 应用控制信息以在从接收到写入命令之后发生第一预定延迟时间之后启动写入操作。 在时钟信号的时钟周期期间，第二多个引脚的每个引脚传送两位读取数据。