公开(公告)号：US06952746B2

公开(公告)日：2005-10-04

申请号：US09881922

申请日：2001-06-14

申请人： Louis Bennie Capps, Jr. ,  Scott Leonard Daniels ,  Bruce Mealey

发明人： Louis Bennie Capps, Jr. ,  Scott Leonard Daniels ,  Bruce Mealey

IPC分类号： G06F3/00 ,  G06F13/00

CPC分类号： G06F11/349

摘要： A method and system for enhancing performance of a bus in a data processing system is described. The method includes monitoring priority of processes in an operating system queue along with data flow through adapters coupled to the bus in a data processing system, determining if increased bus performance is desirable, and adjusting bus parameters to enhance the performance of the bus if increased bus performance is desirable.

摘要翻译： 描述了一种用于增强数据处理系统中总线性能的方法和系统。 该方法包括监视操作系统队列中的进程的优先级以及通过耦合到数据处理系统中的总线的适配器的数据流，确定是否需要增加总线性能，以及调整总线参数以增强总线的性能，如果增加总线 性能是可取的。

公开(公告)号：US5819095A

公开(公告)日：1998-10-06

申请号：US769844

申请日：1996-12-20

申请人： Louis Bennie Capps, Jr. ,  Son Hung Lam ,  An Xuan Tra

发明人： Louis Bennie Capps, Jr. ,  Son Hung Lam ,  An Xuan Tra

IPC分类号： G06F13/24 ,  G06F13/14 ,  G06F9/46

CPC分类号： G06F13/24

摘要： A method and apparatus of making a computer system using the peripheral component interconnect (PCI) bus architecture compatible with an Apple computer system are provided. In a preferred embodiment mechanism is used for dedicating interrupt request lines to each of a plurality of input/output (I/O) devices, a mechanism for providing an interrupt request from one of the plurality of I/O devices to a processor, and a mechanism for disabling an interrupt controller on the motherboard of the system (or onboard interrupt controller) so as to allow an interrupt controller residing on an Apple adapter to control the system. The interrupt controller on the Apple adapter contains an input for each of the various I/O adapters attached to the computer system and also provides a request line to the processor.

摘要翻译： 提供了使用与Apple计算机系统兼容的外围组件互连（PCI）总线架构来制造计算机系统的方法和装置。 在优选实施例中，机制用于将中断请求线专用于多个输入/输出（I / O）设备中的每一个，用于将多个I / O设备之一的中断请求提供给处理器的机制，以及 一种用于禁用系统（或板载中断控制器）主板上的中断控制器的机制，以允许驻留在Apple适配器上的中断控制器来控制系统。 Apple适配器上的中断控制器包含连接到计算机系统的各种I / O适配器的输入，并为处理器提供请求线。

公开(公告)号：US09881099B2

公开(公告)日：2018-01-30

申请号：US12786072

申请日：2010-05-24

申请人： Robert H. Bell, Jr. ,  Louis Bennie Capps, Jr. ,  Danie M. Dreps ,  Luis A Lastras-Montano ,  Michael J Shapiro

发明人： Robert H. Bell, Jr. ,  Louis Bennie Capps, Jr. ,  Danie M. Dreps ,  Luis A Lastras-Montano ,  Michael J Shapiro

IPC分类号： G06F17/30 ,  G06F12/00 ,  G06K9/62

CPC分类号： G06F17/30899 ,  G06F17/30259 ,  G06K9/6202

摘要： According to one aspect of the present disclosure a method and technique for managing data transfer is disclosed. The method includes comparing, by a processor unit of a data processing system, data to be written to a memory subsystem to a stored data pattern and, responsive to determining that the data matches the stored data pattern, replacing the matching data with a pattern tag corresponding to the matching data pattern. The method also includes transmitting the pattern tag to the memory subsystem.

公开(公告)号：US20130013903A1

公开(公告)日：2013-01-10

申请号：US13613936

申请日：2012-09-13

申请人： Robert H. Bell, JR. ,  Louis Bennie Capps, JR. ,  Thomas Edward Cook ,  Glenn G. Daves ,  Ronald Edward Newhart ,  Michael A. Paolini ,  Michael Jay Shapiro

发明人： Robert H. Bell, JR. ,  Louis Bennie Capps, JR. ,  Thomas Edward Cook ,  Glenn G. Daves ,  Ronald Edward Newhart ,  Michael A. Paolini ,  Michael Jay Shapiro

IPC分类号： G06F9/06

CPC分类号： G06F15/7871

摘要： A processor has multiple cores with each core having an associated function to support processor operations. The functions performed by the cores are selectively altered to improve processor operations by balancing the resources applied for each function. For example, each core comprises a field programmable array that is selectively and dynamically programmed to perform a function, such as a floating point function or a fixed point function, based on the number of operations that use each function. As another example, a processor is built with a greater number of cores than can be simultaneously powered, each core associated with a function, so that cores having functions with lower utilization are selectively powered down.

摘要翻译： 处理器具有多个核心，每个核心具有相关功能以支持处理器操作。 通过平衡应用于每个功能的资源，选择性地改变由核执行的功能以改善处理器操作。 例如，每个核心包括一个现场可编程阵列，该阵列可以根据使用每个功能的操作次数，选择性地和动态地编程来执行诸如浮点函数或固定点功能的功能。 作为另一示例，处理器被构建为具有比可以同时供电的更多数量的核，每个核与功能相关联，使得具有较低利用率的功能的核被选择性地关机。

公开(公告)号：US20110289270A1

公开(公告)日：2011-11-24

申请号：US12786072

申请日：2010-05-24

申请人： Robert H. Bell, JR. ,  Louis Bennie Capps, JR. ,  Daniel M. Dreps ,  Luis A. Lastras-Montano ,  Michael Jay Shapiro

发明人： Robert H. Bell, JR. ,  Louis Bennie Capps, JR. ,  Daniel M. Dreps ,  Luis A. Lastras-Montano ,  Michael Jay Shapiro

IPC分类号： G06F17/30 ,  G06F12/00

CPC分类号： G06F17/30899 ,  G06F17/30259 ,  G06K9/6202

摘要： According to one aspect of the present disclosure a method and technique for managing data transfer is disclosed. The method includes comparing, by a processor unit of a data processing system, data to be written to a memory subsystem to a stored data pattern and, responsive to determining that the data matches the stored data pattern, replacing the matching data with a pattern tag corresponding to the matching data pattern. The method also includes transmitting the pattern tag to the memory subsystem.

摘要翻译： 根据本公开的一个方面，公开了一种用于管理数据传送的方法和技术。 该方法包括将由数据处理系统的处理器单元将要写入存储器子系统的数据与存储的数据模式进行比较，并且响应于确定数据与存储的数据模式匹配，用模式标签替换匹配数据 对应于匹配的数据模式。 该方法还包括将模式标签发送到存储器子系统。

公开(公告)号：US20100049963A1

公开(公告)日：2010-02-25

申请号：US12197357

申请日：2008-08-25

申请人： Robert H. Bell, JR. ,  Louis Bennie Capps, JR. ,  Thomas Edward Cook ,  Glenn G. Daves ,  Ronald Edward Newhart ,  Michael A. Paolini ,  Michael Jay Shapiro

发明人： Robert H. Bell, JR. ,  Louis Bennie Capps, JR. ,  Thomas Edward Cook ,  Glenn G. Daves ,  Ronald Edward Newhart ,  Michael A. Paolini ,  Michael Jay Shapiro

IPC分类号： G06F9/00

CPC分类号： G06F15/7871

摘要： A processor has multiple cores with each core having an associated function to support processor operations. The functions performed by the cores are selectively altered to improve processor operations by balancing the resources applied for each function. For example, each core comprises a field programmable array that is selectively and dynamically programmed to perform a function, such as a floating point function or a fixed point function, based on the number of operations that use each function. As another example, a processor is built with a greater number of cores than can be simultaneously powered, each core associated with a function, so that cores having functions with lower utilization are selectively powered down.

摘要翻译： 处理器具有多个核心，每个核心具有相关功能以支持处理器操作。 通过平衡应用于每个功能的资源，选择性地改变由核执行的功能以改善处理器操作。 例如，每个核心包括一个现场可编程阵列，该阵列可以根据使用每个功能的操作次数，选择性地和动态地编程来执行诸如浮点函数或固定点功能的功能。 作为另一示例，处理器被构建为具有比可以同时供电的更多数量的核，每个核与功能相关联，使得具有较低利用率的功能的核被选择性地关机。

公开(公告)号：US07584369B2

公开(公告)日：2009-09-01

申请号：US11460014

申请日：2006-07-26

申请人： Louis Bennie Capps, Jr. ,  Warren D. Dyckman ,  Michael Jay Shapiro

发明人： Louis Bennie Capps, Jr. ,  Warren D. Dyckman ,  Michael Jay Shapiro

IPC分类号： G06F1/00 ,  G06F15/00 ,  G06F15/16

CPC分类号： G06F1/206

摘要： The disclosed methodology and apparatus may control heat generation in a multi-core processor. In one embodiment, each processor core includes a temperature sensor that reports temperature information to a processor controller. If a particular processor core exceeds a predetermined temperature, the processor core disables that processor core to allow it to cool. The processor core enables the previously disabled processor when the previously disabled processor core cools sufficiently to a normal operating temperature. The disclosed multi-core processor may avoid undesirable hot spots that impact processor life.

摘要翻译： 所公开的方法和装置可以控制多核处理器中的发热。 在一个实施例中，每个处理器核心包括将温度信息报告给处理器控制器的温度传感器。 如果特定处理器核心超过预定温度，则处理器内核禁用该处理器核心以使其冷却。 当先前禁用的处理器内核足够冷却至正常工作温度时，处理器内核可以启用先前禁用的处理器。 所公开的多核处理器可以避免影响处理器寿命的不期望的热点。

公开(公告)号：US20090164759A1

公开(公告)日：2009-06-25

申请号：US11959821

申请日：2007-12-19

申请人： Robert H. Bell, JR. ,  Louis Bennie Capps, JR. ,  Michael A. Paolini ,  Michael Jay Shapiro

发明人： Robert H. Bell, JR. ,  Louis Bennie Capps, JR. ,  Michael A. Paolini ,  Michael Jay Shapiro

IPC分类号： G06F9/30

CPC分类号： G06F9/3842 ,  G06F9/3851 ,  G06F9/505 ,  G06F2209/5017

摘要： A method and apparatus for speculatively executing a single threaded program within a multi-core processor which includes identifying an idle core within the multi-core processor, performing a look ahead operation on the single thread instructions to identify speculative instructions within the single thread instructions, and allocating the idle core to execute the speculative instructions.

摘要翻译： 一种用于在多核处理器内推测性地执行单线程程序的方法和装置，其包括识别所述多​​核处理器内的空闲核心，对所述单线程指令执行向前操作以识别所述单线程指令内的推测指令， 并分配空闲核心以执行推测性指令。

公开(公告)号：US07472297B2

公开(公告)日：2008-12-30

申请号：US11304956

申请日：2005-12-15

申请人： Louis Bennie Capps, Jr. ,  Mark Elliott Hack ,  Steven Paul Hartman ,  Michael Jay Shapiro

发明人： Louis Bennie Capps, Jr. ,  Mark Elliott Hack ,  Steven Paul Hartman ,  Michael Jay Shapiro

IPC分类号： G06F1/26

CPC分类号： G06F1/206

摘要： A method for automatically initializing the operational settings of a system from information stored within a non-volatile storage of an integrated circuit so that the operational requirements of the integrated circuit, which may be a microprocessor, are met by the system when the system is operating. During manufacturing test, environmental requirements of the integrated circuit are determined and stored within the non-volatile storage of the integrated circuit. During system initialization, environmental control values such as required operating voltage and frequency and cooling requirements are determined from the test values, which are read from the integrated circuit. The values are read by an interface of the system from an interface of the integrated circuit. System settings are controlled by the values to provide the required operating environment and the values may be captured within the system for subsequent operations and initialization sequences.

摘要翻译： 一种用于根据存储在集成电路的非易失性存储器中的信息自动初始化系统的操作设置的方法，使得当系统运行时系统满足可能是微处理器的集成电路的操作要求 。 在制造测试期间，集成电路的环境要求被确定并存储在集成电路的非易失性存储器中。 在系统初始化期间，从集成电路读取的测试值确定所需的工作电压，频率和冷却要求等环境控制值。 这些值由系统的接口从集成电路的接口读取。 系统设置由值控制以提供所需的操作环境，并且可以在系统内捕获值以用于后续操作和初始化序列。

公开(公告)号：US06665782B2

公开(公告)日：2003-12-16

申请号：US09931430

申请日：2001-08-16

申请人： Louis Bennie Capps, Jr. ,  Scott Leonard Daniels ,  Danny Marvin Neal ,  Yat Hung Ng

发明人： Louis Bennie Capps, Jr. ,  Scott Leonard Daniels ,  Danny Marvin Neal ,  Yat Hung Ng

IPC分类号： G06F1200

CPC分类号： G06F21/79 ,  G06F21/85 ,  G11C7/24

摘要： A method and apparatus for preventing unauthorized access to data stored in memory utilizing two programmable logic devices as front end interfaces for the memory device and the data processing device which is to utilize the memory device, respectively. The two programmable logic devices are complementary programmed such that the signal lines between the data processing device and the memory core and/or their timing are scrambled at the interface between the two programmable logic devices, but are properly ordered with the proper timing at the interface between the memory core and the first programmable logic device and the interface between the data processing device and the second programmable logic device.

摘要翻译： 一种方法和装置，用于分别使用两个可编程逻辑器件作为用于存储器件的前端接口和要利用该存储器件的数据处理器件，来存储存储在存储器中的数据。 两个可编程逻辑器件是互补编程的，使得数据处理器件和存储器核心之间的信号线和/或它们的定时在两个可编程逻辑器件之间的接口处被加扰，但是在接口处适当地按正确的时序排序 在存储器核心和第一可编程逻辑器件之间以及数据处理器件和第二可编程逻辑器件之间的接口。