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    Quantum-well-based semiconductor devices
    21.
    发明授权
    Quantum-well-based semiconductor devices 有权
    量子阱半导体器件

    公开(公告)号：US08536621B2

    公开(公告)日：2013-09-17

    申请号：US13571121

    申请日：2012-08-09

    Applicant: Gilbert Dewey ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Robert S. Chau ,  Matthew V. Metz

    Inventor： Gilbert Dewey ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Robert S. Chau ,  Matthew V. Metz

    IPC: H01L29/66

    CPC classification number: H01L29/66666 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783

    Abstract: Quantum-well-based semiconductor devices and methods of forming quantum-well-based semiconductor devices are described. A method includes providing a hetero-structure disposed above a substrate and including a quantum-well channel region. The method also includes forming a source and drain material region above the quantum-well channel region. The method also includes forming a trench in the source and drain material region to provide a source region separated from a drain region. The method also includes forming a gate dielectric layer in the trench, between the source and drain regions; and forming a gate electrode in the trench, above the gate dielectric layer.

    Abstract translation: 描述了基于量子阱的半导体器件和形成量子阱基半导体器件的方法。 一种方法包括提供设置在衬底上方并包括量子阱沟道区的异质结构。 该方法还包括在量子阱沟道区上方形成源极和漏极材料区域。 该方法还包括在源极和漏极材料区域中形成沟槽以提供与漏极区域分离的源极区域。 该方法还包括在沟槽中，在源极和漏极区之间形成栅极电介质层; 以及在所述沟槽中形成栅电极，在所述栅介质层上方。

    Modulation-doped multi-gate devices
    23.
    发明授权
    Modulation-doped multi-gate devices 有权
    调制掺杂多栅极器件

    公开(公告)号：US08350291B2

    公开(公告)日：2013-01-08

    申请号：US13248197

    申请日：2011-09-29

    Applicant: Mantu K. Hudait ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Jack T. Kavalieros

    Inventor： Mantu K. Hudait ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Jack T. Kavalieros

    IPC: H01L29/78

    CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/66795

    Abstract: Modulation-doped multi-gate devices are generally described. In one example, an apparatus includes a semiconductor substrate having a surface, one or more buffer films coupled to the surface of the semiconductor substrate, a first barrier film coupled to the one or more buffer films, a multi-gate fin coupled to the first barrier film, the multi-gate fin comprising a source region, a drain region, and a channel region of a multi-gate device wherein the channel region is disposed between the source region and the drain region, a spacer film coupled to the multi-gate fin, and a doped film coupled to the spacer film.

    Abstract translation: 通常描述调制掺杂多栅极器件。 在一个示例中，设备包括具有表面的半导体衬底，耦合到半导体衬底的表面的一个或多个缓冲膜，耦合到该一个或多个缓冲膜的第一阻挡膜，耦合到第一 所述多栅极鳍片包括源极区域，漏极区域和多栅极器件的沟道区域，其中所述沟道区域设置在所述源极区域和所述漏极区域之间，间隔膜耦合到所述多栅极器件， 栅极鳍片以及耦合到间隔膜的掺杂膜。

    Semiconductor heterostructures to reduce short channel effects
    25.
    发明授权
    Semiconductor heterostructures to reduce short channel effects 有权
    半导体异质结构减少短路效应

    公开(公告)号：US08278687B2

    公开(公告)日：2012-10-02

    申请号：US12058101

    申请日：2008-03-28

    Applicant: Ravi Pillarisetty ,  Mantu K. Hudait ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Robert S. Chau

    Inventor： Ravi Pillarisetty ,  Mantu K. Hudait ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Robert S. Chau

    IPC: H01L29/778

    CPC classification number: H01L29/7783 ,  H01L29/42316 ,  H01L29/7784

    Abstract: Semiconductor heterostructures to reduce short channel effects are generally described. In one example, an apparatus includes a semiconductor substrate, one or more buffer layers coupled to the semiconductor substrate, a first barrier layer coupled to the one or more buffer layers, a back gate layer coupled to the first barrier layer wherein the back gate layer includes a group III-V semiconductor material, a group II-VI semiconductor material, or combinations thereof, the back gate layer having a first bandgap, a second barrier layer coupled to the back gate layer wherein the second barrier layer includes a group III-V semiconductor material, a group II-VI semiconductor material, or combinations thereof, the second barrier layer having a second bandgap that is relatively larger than the first bandgap, and a quantum well channel coupled to the second barrier layer, the quantum well channel having a third bandgap that is relatively smaller than the second bandgap.

    Abstract translation: 通常描述用于减少短通道效应的半导体异质结构。 在一个示例中，设备包括半导体衬底，耦合到半导体衬底的一个或多个缓冲层，耦合到一个或多个缓冲层的第一势垒层，耦合到第一阻挡层的背栅层，其中背栅层 包括III-V族半导体材料，II-VI族半导体材料或其组合，所述背栅层具有第一带隙，耦合到所述背栅层的第二阻挡层，其中所述第二阻挡层包括III- V族半导体材料，II-VI族半导体材料或其组合，所述第二阻挡层具有相对大于所述第一带隙的第二带隙，以及耦合到所述第二阻挡层的量子阱沟道，所述量子阱沟道具有 相对小于第二带隙的第三带隙。

    Quantum-well-based semiconductor devices
    27.
    发明授权
    Quantum-well-based semiconductor devices 有权
    量子阱半导体器件

    公开(公告)号：US08258543B2

    公开(公告)日：2012-09-04

    申请号：US12632498

    申请日：2009-12-07

    Applicant: Gilbert Dewey ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Robert S. Chau ,  Matthew V. Metz

    Inventor： Gilbert Dewey ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Robert S. Chau ,  Matthew V. Metz

    IPC: H01L29/66

    CPC classification number: H01L29/66666 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783

    Abstract: Quantum-well-based semiconductor devices and methods of forming quantum-well-based semiconductor devices are described. A method includes providing a hetero-structure disposed above a substrate and including a quantum-well channel region. The method also includes forming a source and drain material region above the quantum-well channel region. The method also includes forming a trench in the source and drain material region to provide a source region separated from a drain region. The method also includes forming a gate dielectric layer in the trench, between the source and drain regions; and forming a gate electrode in the trench, above the gate dielectric layer.

    Abstract translation: 描述了基于量子阱的半导体器件和形成量子阱基半导体器件的方法。 一种方法包括提供设置在衬底上方并包括量子阱沟道区的异质结构。 该方法还包括在量子阱沟道区上方形成源极和漏极材料区域。 该方法还包括在源极和漏极材料区域中形成沟槽以提供与漏极区域分离的源极区域。 该方法还包括在沟槽中，在源极和漏极区之间形成栅极电介质层; 以及在所述沟槽中形成栅电极，在所述栅介质层上方。

    QUANTUM-WELL-BASED SEMICONDUCTOR DEVICES
    30.
    发明申请
    QUANTUM-WELL-BASED SEMICONDUCTOR DEVICES 有权
    基于量子阱的半导体器件

    公开(公告)号：US20110133168A1

    公开(公告)日：2011-06-09

    申请号：US12632498

    申请日：2009-12-07

    Applicant: Gilbert Dewey ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Robert S. Chau ,  Matthew V. Metz

    Inventor： Gilbert Dewey ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Robert S. Chau ,  Matthew V. Metz

    IPC: H01L29/12 ,  H01L21/336

    CPC classification number: H01L29/66666 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783

    Abstract: Quantum-well-based semiconductor devices and methods of forming quantum-well-based semiconductor devices are described. A method includes providing a hetero-structure disposed above a substrate and including a quantum-well channel region. The method also includes forming a source and drain material region above the quantum-well channel region. The method also includes forming a trench in the source and drain material region to provide a source region separated from a drain region. The method also includes forming a gate dielectric layer in the trench, between the source and drain regions; and forming a gate electrode in the trench, above the gate dielectric layer.

    Abstract translation: 描述了基于量子阱的半导体器件和形成量子阱基半导体器件的方法。 一种方法包括提供设置在衬底上方并包括量子阱沟道区的异质结构。 该方法还包括在量子阱沟道区上方形成源极和漏极材料区域。 该方法还包括在源极和漏极材料区域中形成沟槽以提供与漏极区域分离的源极区域。 该方法还包括在沟槽中，在源极和漏极区之间形成栅极电介质层; 以及在所述沟槽中形成栅电极，在所述栅介质层上方。

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