METHOD OF MONITORING A SERVER RACK SYSTEM, AND THE SERVER RACK SYSTEM

    公开(公告)号:US20170324636A1

    公开(公告)日:2017-11-09

    申请号:US15150275

    申请日:2016-05-09

    Inventor: Po-Wei WANG

    Abstract: A method of monitoring a server rack system includes: initializing each of a rack management controller (RMC), a rack back plate (RBP) and a baseboard management controller (BMC); transmitting by the RMC an initiation message to RBP; transmitting by the RBP initiation messages to the BMC and the RMC, respectively; transmitting by the BMC an initiation message to RBP transmitting by the BMC a real-time monitoring output associated with a condition of a server to the RBP after receiving the initiation message transmitted by the RBP; and transmitting by the RBP at least a portion of the real-time monitoring output received from the BMC to the RMC after receiving the initiation message transmitted by the RMC.

    METHOD OF DETECTING POWER RESET OF A SERVER, A BASEBOARD MANAGEMENT CONTROLLER, AND A SERVER

    公开(公告)号:US20170220419A1

    公开(公告)日:2017-08-03

    申请号:US15014073

    申请日:2016-02-03

    Inventor: Ming-I KUO

    CPC classification number: G06F11/1417 G06F11/0721 G06F11/0757 G06F11/079

    Abstract: A method of detecting power reset of a server includes: after receiving an event signal, determining whether or not to initialize a random access memory (RAM) of a baseboard management controller (BMC) of the server based on the event signal thus received, and initializing the RAM when it is determined to initialize the same; determining whether a protocol error event has occurred according to a flag value of a power reset flag stored in the RAM; determining whether malfunction of a processor unit of the BMC has occurred when it is determined that the protocol error event has not occurred; and determining that a power reset event has occurred when it is determined that malfunction of the processor unit has not occurred.

    METHOD AND SYSTEM FOR PERFORMING AUTOMATIC SYSTEM RECOVERY
    24.
    发明申请
    METHOD AND SYSTEM FOR PERFORMING AUTOMATIC SYSTEM RECOVERY 有权
    执行自动系统恢复的方法和系统

    公开(公告)号:US20170052854A1

    公开(公告)日:2017-02-23

    申请号:US15238344

    申请日:2016-08-16

    Inventor: Shun-Chieh YANG

    Abstract: A method for performing automatic system recovery is implemented by a server including a control chipset and a baseboard management controller (BMC). In the method, when a current image file is corrupted, a recovery engine generates an indicator of a version of the current image file and transmits the indicator to the BMC. The BMC then transmits a request for a backup image file to an external electronic device. After the BMC receives file link information of a disk image file from the electronic device, the BMC accesses the electronic device to download the disk image file, and mounts the disk image file as a virtual disk on the BMC. Afterward, the recovery engine replaces the current image file with the disk image file from the virtual disk.

    Abstract translation: 用于执行自动系统恢复的方法由包括控制芯片组和基板管理控制器(BMC)的服务器实现。 在该方法中,当当前图像文件被破坏时,恢复引擎生成当前图像文件的版本的指示符,并将该指示符发送给BMC​​。 然后,BMC向外部电子设备发送备份映像文件的请求。 BMC从电子设备收到磁盘映像文件的文件链接信息后,BMC访问电子设备下载磁盘映像文件,并将磁盘映像文件作为虚拟磁盘安装在BMC上。 之后,恢复引擎将使用虚拟磁盘的磁盘映像文件替换当前映像文件。

    POWER MANAGEMENT METHOD
    25.
    发明公开

    公开(公告)号:US20240353908A1

    公开(公告)日:2024-10-24

    申请号:US18617254

    申请日:2024-03-26

    CPC classification number: G06F1/30 G06F1/263

    Abstract: A power management method is adapted for a computer system that includes a CPU, a control unit, a BIOS and multiple PSUs. When one PSU operates abnormally, it sends an alert signal that is in an alert state to the control unit, and the control unit causes the CPU to operate under a predefined lowest power consumption limit. The control unit computes an updated power consumption limit, and notifies the BIOS to write the updated power consumption limit into a model-specific register of the CPU, so as to make the CPU operate under the updated power consumption limit.

    Method for reading information from riser cards and baseboard management control module implementing the same

    公开(公告)号:US12061565B2

    公开(公告)日:2024-08-13

    申请号:US18184506

    申请日:2023-03-15

    Inventor: Chih-Wei Lee

    CPC classification number: G06F13/409 G06F1/185

    Abstract: A method for reading information from multiple riser cards is implemented by a BMC module that includes an SMBus controller, where the riser cards are electrically connected to the SMBus controller. The method includes steps of: accessing a lookup table and a plurality of bus addresses; scanning a target address for communicating with a target card; determining whether a slave address has been received from the target card; when the BMC module determines that the slave address has been received from the target card, reading a memory of the target card according to a target reading spec to obtain identification information; determining whether the identification information conforms to an FRU header format; and when the BMC module determines that the identification information conforms to the FRU header format, reading the memory of the target card to obtain FRU information.

    High availability system and input/output module (IOM) assembly

    公开(公告)号:US12056357B2

    公开(公告)日:2024-08-06

    申请号:US18166998

    申请日:2023-02-09

    Inventor: Yu-Shu Yeh

    CPC classification number: G06F3/061 G06F3/0655 G06F3/0679

    Abstract: An HA system includes a first IOM having a first switch, a second IOM having a second switch, and a plurality of slot modules configured to be connected to a plurality of SSDs, respectively. Each of the slot modules has Port A′ configured to be connected to the first IOM and Port B′ configured to be connected to the second IOM. In response to detecting a connection of one of the SSDs to one of the slot modules, the first and second IOMs determine whether the SSD is a single-port type SSD. When it is determined that the SSD is a single-port type SSD, the first IOM controls the first switch to link up to said one of the slot modules and the second IOM controls the second switch to unlink said one of the slot modules.

    COMPUTER AND METHOD OF BOOTING COMPUTER
    28.
    发明公开

    公开(公告)号:US20240231835A9

    公开(公告)日:2024-07-11

    申请号:US18491325

    申请日:2023-10-20

    Inventor: Hsin-I Lee

    CPC classification number: G06F9/441

    Abstract: A method of booting a computer is provided. The computer includes a processing unit, and a baseboard controlling unit storing a prioritized option of boot device and a prioritized type of boot hard disk. The method includes steps of: the processing unit sending a first query about the prioritized option of boot device to the baseboard controlling unit; in response to receiving the prioritized option of boot device from the baseboard controlling unit, when the processing unit determines that the prioritized option of boot device is hard disk, the processing unit sending a second query about the prioritized type of boot hard disk to the baseboard controlling unit; and in response to receiving the prioritized type of boot hard disk from the baseboard controlling unit, the processing unit booting the computer from a hard disk that corresponds to the prioritized type of boot hard disk.

    METHOD OF MONITORING CLOCK SIGNAL OF SERVER
    29.
    发明公开

    公开(公告)号:US20240146501A1

    公开(公告)日:2024-05-02

    申请号:US18219870

    申请日:2023-07-10

    CPC classification number: H04L7/0331

    Abstract: A method of monitoring a clock signal of a server is provided. The server includes a phase-locked loop (PLL), a baseboard management controller (BMC), and a light emitting unit. The method includes steps of: A) the server executing a time synchronization service to obtain a synchronization mode that the PLL is operating in, where the synchronization mode is one of a free-run mode, a locked mode, and a holdover mode; B) the server updating the synchronization mode to the BMC when executing the time synchronization service; and C) the BMC storing the synchronization mode and controlling the light emitting unit to display in one of a plurality of displaying manners that corresponds to the synchronization mode.

    SYNCHRONIZING SYSTEM FOR TIME SYNCHRONIZATION REQUIRED FOR DATA TRANSCEIVER CONTROL

    公开(公告)号:US20240120928A1

    公开(公告)日:2024-04-11

    申请号:US18470790

    申请日:2023-09-20

    CPC classification number: H03L7/099

    Abstract: A synchronizing system includes a phase-locked loop (PLL), first and second network controllers (NCs), a retimer and a processor. The PLL receives a local oscillator (LO) signal, generates and outputs a clock signal and a synchronizing signal. The retimer and the first and second NCs operate according to the clock signal. The first/second NC generates a first/second clock-event signal based on the synchronizing signal. The processor generates a first/second Precision Time Protocol (PTP) signal based on the first/second clock-event signal, and transmits the first/second PTP signal to the first/second NC. The second NC delivers the second PTP signal to first transceivers. The retimer performs retiming on the first PTP signal, and delivers the same to second transceivers. In a master mode, the PLL unit generates the synchronizing signal based on the LO signal and a reference time signal received from a global navigation satellite system (GNSS).

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