公开(公告)号：US12302585B2

公开(公告)日：2025-05-13

申请号：US17805586

申请日：2022-06-06

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Ashonita A. Chavan

IPC: H10B53/30 ,  H10B51/10 ,  H10B51/30 ,  H10B53/10

Abstract: Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, a memory device includes multiple memory cells. Each memory cell may include a bottom electrode having an open top cylinder shape that contains a support pillar, may include a top electrode, may include an insulator that separates the top electrode from the bottom electrode, and may include a leaker device having an open top cylinder shape. A bottom surface of the leaker device may abut at least one of a top surface of the bottom electrode or a top surface of the support pillar. A top surface of the leaker device may abut a bottom surface of a conductive plate. The memory device may also include the conductive plate.

公开(公告)号：US12301713B2

公开(公告)日：2025-05-13

申请号：US18743476

申请日：2024-06-14

Applicant: Micron Technology, Inc.

Inventor： Luca Bert ,  Joseph Harold Steinmetz

IPC: H04L9/08 ,  G06F3/06 ,  H04L9/30 ,  G06F21/60 ,  G06F21/79 ,  H04L9/00 ,  H04L9/32

Abstract: A security server storing a plurality of cryptographic keys to support device authentication, access control and proof of space plot farming. The cryptographic keys can include a first cryptographic key representative of an identity of a memory device, a second cryptographic key representative of a privilege to access a memory region in the memory device, and a third cryptographic key representative of a pool of proof of space plots. The security server can sign blocks in a blockchain created via plots in the pool, sign commands to access the memory region, and secure transfer of the second and/or third cryptographic key to the computer operated by an owner of the memory device.

公开(公告)号：US12301254B2

公开(公告)日：2025-05-13

申请号：US17829913

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Eyal En Gad ,  Mustafa N. Kaynak ,  Yoav Weinberg ,  Zhengang Chen ,  Sivagnanam Parthasarathy

IPC: H03M13/11

Abstract: A processing device in a memory sub-system determines a syndrome weight for a sense word read from a memory device and determines whether the syndrome weight for the sense word satisfies a threshold criterion. Responsive to the syndrome weight for the sense word satisfying a respective threshold criterion associated with a next iteration of a first decoding operation, bypassing the first decoding operation and initiating a second decoding operation for the sense word, wherein the second decoding operation has a higher error correction capability than the first decoding operation.

公开(公告)号：US12300736B2

公开(公告)日：2025-05-13

申请号：US18101120

申请日：2023-01-25

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L21/00 ,  H01L29/40 ,  H01L29/51 ,  H01L29/78 ,  H10B12/00 ,  H10B53/10 ,  H10B53/20 ,  H10B53/30 ,  H01L29/24 ,  H10B53/40

Abstract: Some embodiments include integrated memory having an array of access transistors. Each access transistor includes an active region which has a first source/drain region, a second source/drain region and a channel region. The active regions of the access transistors include semiconductor material having elements selected from Groups 13 and 16 of the periodic table. First conductive structures extend along rows of the array and have gating segments adjacent the channel regions of the access transistors. Heterogenous insulative regions are between the gating segments and the channel regions. Second conductive structures extend along columns of the array, and are electrically coupled with the first source/drain regions. Storage-elements are electrically coupled with the second source/drain regions. Some embodiments include a transistor having a semiconductor oxide channel material. A conductive gate material is adjacent to the channel material. A heterogenous insulative region is between the gate material and the channel material.

公开(公告)号：US12300570B2

公开(公告)日：2025-05-13

申请号：US17583038

申请日：2022-01-24

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street ,  Kyle K. Kirby

IPC: H01L23/373 ,  H01L21/56 ,  H01L21/603 ,  H01L23/31 ,  H01L23/544 ,  H01L25/16

Abstract: A semiconductor package can include a semiconductor die stack including a top die and one or more core dies below the top die. The semiconductor package can further include a metal heat sink plated on a top surface of the top die and have a plurality of side surfaces coplanar with corresponding ones of a plurality of sidewalls of the semiconductor die stack. A molding can surround the stack of semiconductor dies and the metal heat sink, the molding including a top surface coplanar with an exposed upper surface of the metal heat sink. The top surface of the molding and the exposed upper surface of the metal heat sink are both mechanically altered. For example, the metal heat sink and the molding can be simultaneously ground with a grinding disc and can show grinding marks as a result.

公开(公告)号：US12299331B2

公开(公告)日：2025-05-13

申请号：US18583540

申请日：2024-02-21

Applicant: Micron Technology, Inc.

Inventor： Nicola Del Gatto ,  Massimiliano Patriarca ,  Antonino Caprì ,  Emanuele Confalonieri ,  Angelo Alberto Rovelli

IPC: G06F3/06

Abstract: Methods, systems, and devices for managed memory systems with multiple priority queues are described. Memory access commands may be received from a host and stored in a command queue. First and second subsets of the commands, respectively associated with first and second priorities, may be determined. The first and second subsets may be routed from the command queue to first and second queues, respectively. The first and second subsets may be processed from the first and second queues to third and fourth queues, respectively, at a storage controller, according to first and second processes that may be run concurrently according to parameters for prioritization between the first and second priorities. Data associated with the commands may be received from the host, temporarily stored in a buffer, then moved to a storage memory (for write commands) or retrieved from the storage memory, temporarily stored in the buffer, then transmitted to the host (for read commands).

公开(公告)号：US12299308B2

公开(公告)日：2025-05-13

申请号：US18395934

申请日：2023-12-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Steven R Narum

IPC: G06F3/06

Abstract: One or more data items is received by a processing device managing one or more memory devices partitioned into a plurality of die partitions. The one or more data items is determined to be written sequentially to one or more blocks within a die partition of the plurality of die partitions. Metadata associated with the one or more data items is written sequentially to one or more blocks across the plurality of die partitions.

公开(公告)号：US12299304B2

公开(公告)日：2025-05-13

申请号：US18746987

申请日：2024-06-18

Applicant: Micron Technology, Inc.

Inventor： Jiangang Wu ,  Jung Sheng Hoei ,  Qisong Lin ,  Kishore Kumar Muchherla

IPC: G06F3/06

Abstract: A processing device access a command to program data to a page in a block of a memory device. The processing device determines whether the page is a last remaining open page in the block. The processing device accesses a list that indicates enablement of a function to apply read level offsets to one or more open blocks in the memory device. The processing device determines the list includes an entry that matches to the block. The entry indicates enablement of the function to apply read level offsets to the block. The processing device disables the function based on determining the page is a last remaining open page in the block. The processing device adds the command to a prioritized queue of commands. The memory device executes commands from the prioritized queue in an order based on a priority level assigned to each command.

公开(公告)号：US12299280B2

公开(公告)日：2025-05-13

申请号：US18598100

申请日：2024-03-07

Applicant: Micron Technology, Inc.

Inventor： Alex Frolikov

IPC: G06F3/06 ,  G06F12/10

Abstract: A computer storage device having a host interface, a controller, non-volatile storage media, and firmware. The firmware instructs the controller to: store a namespace map mapping blocks of logical block addresses in a namespace to blocks from a logical address capacity of the non-volatile storage media; adjust the namespace map to change the size of the namespace; and translate logical addresses in the namespace to physical addresses for the non-volatile storage media using the namespace map.

公开(公告)号：US12298917B2

公开(公告)日：2025-05-13

申请号：US17485166

申请日：2021-09-24

Applicant: Micron Technology, Inc.

Inventor： Jeffrey Charles Shiner ,  Lance W. Dover ,  Olivier Duval

IPC: G06F12/14 ,  G06F21/79

Abstract: A security server to provide security services over a computer network based on security features of memory devices connected to host systems. For example, the security features of a memory device can include a unique device secret, a cryptographic engine, and an access controller to implement access privileges represented by cryptographic keys. After receiving identity data that is generated by the memory device and represented by a cryptographic key, the security server can determine authenticity of the memory device based on its copy of the unique device secret of the memory device. The security server can generate a verification code for a command and cause the command and the verification code to be communicated to the memory device, where the access controller of the memory device validates the verification code in determining whether to block execution of the command in the memory device.