公开(公告)号：US06709979B2

公开(公告)日：2004-03-23

申请号：US09866940

申请日：2001-05-29

Applicant: Naoki Komai ,  Takeshi Nogami ,  Hideyuki Kito ,  Mitsuru Taguchi ,  Katsumi Ando

Inventor： Naoki Komai ,  Takeshi Nogami ,  Hideyuki Kito ,  Mitsuru Taguchi ,  Katsumi Ando

IPC: H01L2144

CPC classification number: H01L21/76873 ,  C23F1/18 ,  H01L21/32115 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/7684 ,  H01L21/76843 ,  H05K3/423

Abstract: A method of implementing an electrolytic polishing process against a wiring-material film by way of preventing excessive polishing or incomplete polishing caused by presence of differential steps locally generated in the objective wiring-material film. The inventive method comprises a step of forming a wiring-material film for burying recessed portions formed on an insulating film formed on a substrate via a plating process; a step of reducing a local differential step generated on the surface of the wiring-material film by way of preserving the wiring material film on the insulating film; and a final step of removing the wiring-material film deposited on the insulating film by way of preserving such wiring-material film deposited, solely inside of the recessed portions.

Abstract translation: 通过防止由于在目标配线材料膜中局部产生的不同步骤的存在而导致的过度抛光或不完全抛光而对布线材料膜实施电解抛光工艺的方法。 本发明的方法包括：通过电镀工艺形成用于掩埋形成在基板上的绝缘膜上的凹部的布线材料膜的步骤; 通过在绝缘膜上保持布线材料膜来减少在布线材料膜的表面上产生的局部差分步骤的步骤; 以及通过保存仅在凹部内部沉积的布线材料膜来去除沉积在绝缘膜上的布线材料膜的最后步骤。

公开(公告)号：US06645852B1

公开(公告)日：2003-11-11

申请号：US09688794

申请日：2000-10-17

Applicant: Mitsuru Taguchi ,  Shingo Kadomura ,  Miyata Koji

Inventor： Mitsuru Taguchi ,  Shingo Kadomura ,  Miyata Koji

IPC: H01L214763

CPC classification number: H01L21/02063 ,  H01L21/31138 ,  H01L21/76807 ,  H01L21/76814 ,  Y10S438/906 ,  Y10S438/974

Abstract: A process for fabricating a semiconductor device, which comprises forming a recess portion in an insulating film covering a wiring made of copper or a copper alloy so that the recess portion reaches the wiring, wherein, after forming the recess portion, a plasma treatment using a gas containing hydrogen gas and nitrogen gas is conducted in a state such that the wiring is exposed through the bottom portion of the recess portion, or a plasma treatment using a gas containing hydrogen gas is conducted in a state such that the wiring is exposed through the bottom portion of the recess portion while cooling a substrate on which the wiring is formed. By the process of the present invention, a problem of redeposition of copper on the sidewall of a via hole in the argon sputtering and a problem of an etching process of the organic insulating film in the hydrogen plasma treatment can be solved, thus realizing excellent cleaning of the bottom portion of the via hole.

Abstract translation: 一种制造半导体器件的方法，包括在覆盖由铜或铜合金制成的布线的绝缘膜中形成凹部，使得凹部到达布线，其中，在形成凹部之后，使用 含有氢气和氮气的气体在使布线通过凹部的底部露出的状态下进行，或者使用含有氢气的气体进行等离子体处理，使得布线通过 同时冷却其上形成有布线的基板。 通过本发明的方法，可以解决在氩溅射中的通孔侧壁上再沉积铜的问题和氢等离子体处理中有机绝缘膜的蚀刻工艺的问题，从而实现优异的清洗 的通孔的底部。

公开(公告)号：US06380065B1

公开(公告)日：2002-04-30

申请号：US09435624

申请日：1999-11-08

Applicant: Naoki Komai ,  Shingo Kadomura ,  Mitsuru Taguchi ,  Akira Yoshio ,  Takaaki Miyamoto

Inventor： Naoki Komai ,  Shingo Kadomura ,  Mitsuru Taguchi ,  Akira Yoshio ,  Takaaki Miyamoto

IPC: H01L214763

CPC classification number: H01L21/76844 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76879

Abstract: In a related interconnection structure that is formed by filling a metal, there have been problems, since defective connection occurs due to generation of voids and other features caused by poor filling of the metal, which entails reduction in reliability, and contact resistance is large due to a barrier metal layer at a contact portion. A novel interconnection structure is provided which comprises: a recess (for example, a contact hole, a trench, or a trench and a contact hole formed at a bottom of the trench), which is connected onto a conductive material mass formed in an insulating film, and which is formed in the insulating film; a barrier metal layer formed on side walls of the recess; and metal material masses filled in the interior of the recess, wherein the metal material masses are formed with a metal repeatedly filled into the recess over a plurality of times, and a metal material mass and a conductive material mass are directly connected to each other.

Abstract translation: 在通过填充金属形成的相关互连结构中，存在问题，因为由于空穴的产生以及由于金属填充不良而引起的其它特征导致了缺陷连接，这导致可靠性降低，并且接触电阻大 到接触部分处的阻挡金属层。 提供了一种新颖的互连结构，其包括：连接到形成在绝缘体中的导电材料块上的凹部（例如，接触孔，沟槽或沟槽以及形成在沟槽的底部的接触孔） 膜，并且其形成在绝缘膜中; 形成在所述凹部的侧壁上的阻挡金属层; 并且填充在凹部内部的金属材料块，其中金属材料质量形成有多次重复填充到凹部中的金属，并且金属材料块和导电材料块彼此直接连接。

公开(公告)号：US06306761B1

公开(公告)日：2001-10-23

申请号：US08637436

申请日：1996-04-25

Applicant: Mitsuru Taguchi

Inventor： Mitsuru Taguchi

IPC: H01L214763

CPC classification number: H01L21/76862 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76882 ,  Y10S438/906

Abstract: A hard Al oxide film having a high melting point, which grows on the surface of an Al—Cu film during a wafer is carried in atmospheric air, obstructs the burying of a viahole with the Al—Cu film by high pressure reflow, with a result that a void remains in the hole. The present invention is intended to remove such an Al oxide film grown on the Al—Cu film formed by sputtering, by Ar+ sputtering/etching directly before high pressure reflow. Moreover, when a Ti oxide film is present on the surface of a Ti based underlying film formed by CVD, an Al oxide film is possibly grown at the boundary between the Ti based underlying film and an Al—Cu film laminated thereon. In this case, the Ti oxide film is similarly removed directly before formation of the Al—Cu film, thereby preventing the growth of the Al oxide film. With this method, it is possible to highly keep thermal flow of a conductive film in a high pressure reflow process, and hence to desirably bury a connection hole with the conductive film.

Abstract translation: 在大气中携带在晶片中在Al-Cu膜的表面生长的具有高熔点的硬质Al氧化物膜，阻碍了通过高压回流与Al-Cu膜的通孔的埋入， 导致孔中留下空隙。 本发明旨在通过在高压回流之前直接进行Ar +溅射/蚀刻来除去在溅射形成的Al-Cu膜上生长的这种Al氧化物膜。 此外，当通过CVD形成的Ti基底层膜的表面上存在Ti氧化物膜时，可能在Ti基底膜和层叠在其上的Al-Cu膜之间的边界处生长Al氧化物膜。 在这种情况下，在形成Al-Cu膜之前，类似地直接除去Ti氧化物膜，从而防止Al氧化物膜的生长。 通过这种方法，可以在高压回流工艺中高度保持导电膜的热流动，因此期望地埋入与导电膜的连接孔。

公开(公告)号：US06191031B1

公开(公告)日：2001-02-20

申请号：US09395596

申请日：1999-09-14

Applicant: Mitsuru Taguchi ,  Shingo Kadomura

Inventor： Mitsuru Taguchi ,  Shingo Kadomura

IPC: H01L214763

CPC classification number: H01L21/76829 ,  H01L21/0332 ,  H01L21/3121 ,  H01L21/76808 ,  H01L2221/1031 ,  H01L2221/1036

Abstract: Upon forming a groove and a connection hole by a dual damascene process, there is a problem in that the connection hole has a bowing shape, and it is difficult to form a shape of the connection hole in a good and stable manner. A process for producing a multi-layer wiring structure is provided, which comprises a step of forming an inter level dielectric film 15 covering a lower layer wiring 14; a step of forming a connection hole 16 in the inter level dielectric film 15 to reach the lower layer wiring 14; a step of forming an inter metal dielectric film 17 filling the connection hole 16 on the inter level dielectric film 15, with an insulating material having an etching rate larger than an etching rate of the inter level dielectric film 15; and a step of forming a concave part 18 in the inter metal dielectric film 17, and selectively re-opening the connection hole 16 with respect to the inter level dielectric film in such a manner that the connection hole is continuous to the concave part 18.

Abstract translation: 在通过双镶嵌工艺形成凹槽和连接孔时，存在连接孔具有弯曲形状的问题，并且难以以良好且稳定的方式形成连接孔的形状。 提供了一种制造多层布线结构的方法，其包括形成覆盖下层布线14的层间电介质膜15的步骤; 在层间电介质膜15中形成连接孔16到达下层布线14的步骤; 用绝缘材料形成填充层间电介质膜15上的连接孔16的金属间电介质膜17的步骤，该绝缘材料的蚀刻速率大于层间电介质膜15的蚀刻速率; 以及在金属间介电膜17中形成凹部18的步骤，并且以连接孔与凹部18连续的方式选择性地重新打开连接孔16相对于层间电介质膜。

公开(公告)号：US5776830A

公开(公告)日：1998-07-07

申请号：US947704

申请日：1997-10-09

Applicant: Hirofumi Sumi ,  Keiichi Maeda ,  Yukiyasu Sugano ,  Kazuhide Koyama ,  Mitsuru Taguchi ,  Kazuhiro Hoshino

Inventor： Hirofumi Sumi ,  Keiichi Maeda ,  Yukiyasu Sugano ,  Kazuhide Koyama ,  Mitsuru Taguchi ,  Kazuhiro Hoshino

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L21/283

CPC classification number: H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76856

Abstract: The present invention provides a process for fabricating a connection structure comprising a anti-reaction layer having excellent barrier properties and having improved ohmic characteristics with respect to the semiconductor substrate. Accordingly, the present invention comprises forming a first anti-reaction layer by temporarily ceasing the film deposition, and then initiating the film deposition again to form a second anti-reaction layer on the surface of the previously deposited first anti-reaction layer. A heat treatment can be applied to the structure after depositing a anti-reaction layer.

Abstract translation: 本发明提供一种制造连接结构的方法，该连接结构包括具有优异的阻挡性能并具有相对于半导体衬底的改善的欧姆特性的抗反应层。 因此，本发明包括通过暂时停止膜沉积来形成第一抗反应层，然后再次引发膜沉积，以在先前沉积的第一抗反应层的表面上形成第二抗反应层。 沉积抗反应层后可以对结构进行热处理。