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    Electrolytic polishing apparatus, electrolytic polishing method and wafer subject to polishing
    2.
    发明授权
    Electrolytic polishing apparatus, electrolytic polishing method and wafer subject to polishing 失效
    电解抛光装置，电解抛光方法和待研磨的晶片

    公开(公告)号：US06736699B2

    公开(公告)日：2004-05-18

    申请号：US09922135

    申请日：2001-08-03

    Applicant: Takeshi Nogami ,  Naoki Komai ,  Hideyuki Kito ,  Mitsuru Taguchi

    Inventor： Takeshi Nogami ,  Naoki Komai ,  Hideyuki Kito ,  Mitsuru Taguchi

    IPC: B24B4900

    CPC classification number: B24B37/013 ,  B24B49/04 ,  C25F3/16 ,  H01L21/67253 ,  Y10S451/908

    Abstract: An electrolytic polishing apparatus for electrolytic-polishing a conductive film subject to formed on a substrate including a resistance measuring unit for measuring the resistance of the film. The electrolytic polishing apparatus may also include a termination point detecting portion for detecting a termination point of polishing by reading a variation of the resistance value measured by the resistance measuring unit, or a polishing control portion for terminating electrolytic polishing on the basis of the termination point of polishing detected by the termination point detecting portion.

    Abstract translation: 一种电解抛光装置，用于对形成在包括用于测量膜的电阻的电阻测量单元的基板上形成的导电膜进行电解抛光。 电解抛光装置还可以包括终止点检测部分，用于通过读取由电阻测量单元测量的电阻值的变化来检测终止点，或者基于终止点来终止电解抛光的抛光控制部分 由终端点检测部分检测到的抛光。

    Method for fabricating semiconductor devices
    3.
    发明授权
    Method for fabricating semiconductor devices 失效

    公开(公告)号：US06602787B2

    公开(公告)日：2003-08-05

    申请号：US09879782

    申请日：2001-06-12

    Applicant: Naoki Komai ,  Takeshi Nogami ,  Hideyuki Kito ,  Mitsuru Taguchi

    Inventor： Naoki Komai ,  Takeshi Nogami ,  Hideyuki Kito ,  Mitsuru Taguchi

    IPC: H01L2144

    CPC classification number: H01L21/76873 ,  H01L21/2885 ,  H01L21/32115 ,  H01L21/32134 ,  H01L21/7684 ,  H01L21/76843

    Abstract: The present invention is to provide a method for fabricating semiconductor devices capable of eliminating a height difference on a base member caused by a residual plating seed layer remained in a portion where an electrode comes into contact and is thus prevented from contacting with an electrolytic polishing fluid, where such height difference has been a problem in introducing the electrolytic polishing process into wafer process. The method comprises the steps of forming a plating seed layer on the base member; forming by the plating process a plated film on the plating seed layer in an area excluding the outer peripheral portion of the base member; polishing the plated film together with the plating seed layer by the electrolytic polishing process; and selectively removing the plating seed layer remaining on the outer peripheral portion of the base member.

    Method for fabricating a semiconductor device in a magnetron sputtering system
    4.
    发明授权
    Method for fabricating a semiconductor device in a magnetron sputtering system 失效
    在磁控溅射系统中制造半导体器件的方法

    公开(公告)号：US06361662B1

    公开(公告)日：2002-03-26

    申请号：US08996321

    申请日：1997-12-22

    Applicant: Yasuhiro Chiba ,  Keiichi Maeda ,  Mitsuru Taguchi

    Inventor： Yasuhiro Chiba ,  Keiichi Maeda ,  Mitsuru Taguchi

    IPC: C23C1434

    CPC classification number: H01L29/665 ,  C23C14/165 ,  C23C14/35 ,  H01J37/3405 ,  H01J37/3426 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/2855

    Abstract: Disclosed is a magnetron sputtering system enabling formation of a film of a ferroelectric substance by suppressing occurrence of a magnetic field due to an eddy current. The magnetron sputtering system includes a flat target; magnetic field applying means (magnets), provided in the vicinity of a back surface of the target, for applying a magnetic field to a front surface of the target; and magnetic field rotating means (motor) for rotating the magnetic field applying means so as to rotate the magnetic field applied to the front surface of the target. The magnetic field rotating means is provided with rotational speed varying means (speed controller) for varying the rotational speed of the magnetic field applied by the magnetic field rotating means.

    Abstract translation: 公开了一种磁控管溅射系统，其能够通过抑制由涡流引起的磁场的产生而形成铁电体的膜。 磁控溅射系统包括平板靶; 设置在所述靶的背面附近的磁场施加装置（磁体），用于向所述目标的前表面施加磁场; 以及用于旋转磁场施加装置的磁场旋转装置（马达），以便旋转施加到目标的前表面的磁场。 磁场旋转装置设置有用于改变由磁场旋转装置施加的磁场的转速的转速改变装置（速度控制器）。

    Semiconductor device manufacturing method
    5.
    发明授权
    Semiconductor device manufacturing method 失效
    半导体器件制造方法

    公开(公告)号：US5985747A

    公开(公告)日：1999-11-16

    申请号：US948526

    申请日：1997-10-09

    Applicant: Mitsuru Taguchi

    Inventor： Mitsuru Taguchi

    IPC: H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/4763

    CPC classification number: H01L21/76843 ,  H01L21/76801 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002

    Abstract: An underlying Al alloy wiring 3 and an inter-layer insulation film 4 are formed sequentially on a semiconductor substrate 1 via an inter-layer insulation film 2. An inter-layer insulation film 5 highly hygroscopic and containing much moisture is made and etched back to flush depressions by the underlying Al alloy wiring 3. After an inter-layer insulation film 6 is made, a contact-hole C is made in the inter-layer insulation films 6 and 4. After that, prior to making a TiN/Ti film 7, gases are removed from the inter-layer insulation films 4 through 6 by annealing. The TiN/Ti film 7 is made as thick as 80 nm. In an alternative version, after the inter-layer insulation film is etched back, annealing is done to remove gases especially from the inter-layer insulation film 5. In another alternative version, a protective film 9 is made on the side wall of the contact-hole C, or the surface of the inter-layer insulation films 6 and 4 having formed the contact-hole or the surface of the inter-layer insulation film 5, is nitrified, to prevent degassing of the inter-layer insulation films 4 through 6.

    Abstract translation: 通过层间绝缘膜2在半导体衬底1上顺序地形成下面的Al合金布线3和层间绝缘膜4.将具有高吸湿性并含有大量水分的层间绝缘膜5制成并回蚀刻 通过下面的Al合金布线3的齐平凹陷。在制成层间绝缘膜6之后，在层间绝缘膜6和4中形成接触孔C.之后，在制造TiN / Ti膜之前 如图7所示，通过退火从层间绝缘膜4〜6除去气体。 TiN / Ti膜7的厚度为80nm。 在替代方案中，在层间绝缘膜被回蚀后，进行退火以特别从层间绝缘膜5去除气体。在另一种替代形式中，在触点的侧壁上形成保护膜9 或者已经形成了接触孔或层间绝缘膜5的表面的层间绝缘膜6和4的表面被硝化，以防止层间绝缘膜4通过 6。

    High-sensitivity differential refractometer
    6.
    发明授权
    High-sensitivity differential refractometer 失效
    高灵敏度差示折光仪

    公开(公告)号：US4126393A

    公开(公告)日：1978-11-21

    申请号：US772212

    申请日：1977-02-25

    Applicant: Sadao Sumikama ,  Shigeru Nakamura ,  Kozo Shirato ,  Kazuo Hiraizumi ,  Nobuo Takasu ,  Mitsuru Taguchi ,  Tsuyoshi Yamada ,  Susumu Ishiguro

    Inventor： Sadao Sumikama ,  Shigeru Nakamura ,  Kozo Shirato ,  Kazuo Hiraizumi ,  Nobuo Takasu ,  Mitsuru Taguchi ,  Tsuyoshi Yamada ,  Susumu Ishiguro

    IPC: G01N21/41 ,  G01N21/46

    CPC classification number: G01N21/4133

    Abstract: Disclosed herein is a high-sensitivity differential refractometer which is characterized by having a light source disposed outside a housing, a reflecting mirror attached at the end portion thereof to a reflecting mirror-supporting plate connected with the end of a movable plate, said movable plate being so constructed as to rotate around a vertical axis and permit free change of the angle formed between said reflecting mirror-supporting plate and the movable plate, a twisting member disposed inside a lead-in tube and said lead-in tube fastened to a removable case and built in a metallic block inside the housing.

    Abstract translation: 本发明公开了一种高灵敏度差示折射计，其特征在于，具有设置在壳体外部的光源，反射镜在其端部附接到与可动板的端部连接的反射镜支撑板，所述可动板 被构造为围绕垂直轴线旋转并且允许在所述反射镜支撑板和可动板之间形成的角度的自由变化，设置在引入管内部的扭转构件，并且所述引入管被固定到可移除的 外壳内装有金属块。

    Method of manufacturing a semiconductor device
    9.
    发明授权
    Method of manufacturing a semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US06333258B1

    公开(公告)日：2001-12-25

    申请号：US09533726

    申请日：2000-03-23

    Applicant: Koji Miyata ,  Toshiaki Hasegawa ,  Mitsuru Taguchi

    Inventor： Koji Miyata ,  Toshiaki Hasegawa ,  Mitsuru Taguchi

    IPC: H01L214763

    CPC classification number: H01L21/76811 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76813

    Abstract: A manufacturing method for forming a dual damascene structure in which the effective permittivity of an inter-layer insulating film is lowered without an etching mask for forming a contact hole, which is otherwise formed in the inter-layer insulating film. The manufacturing method comprises the step of forming an inorganic film to serve as an etching mask, on the inter-layer insulating film; the step of forming a first opening pattern for forming a wiring groove, in an upper part of the inorganic film; and the step of forming a second opening pattern for forming a contact hole, so as to coincide with the first opening pattern at least partially. Further, the contact hole is formed in the inter-layer insulating film by employing an etching mask made of the inorganic film, the inorganic film is etched into a state where only a third opening pattern obtained by transferring the first opening pattern is formed, and a wiring groove is formed in the inter-layer insulating film by employing the resulting inorganic film as the etching mask.

    Abstract translation: 一种用于形成双镶嵌结构的制造方法，其中层间绝缘膜的有效介电常数降低，而没有用于形成在层间绝缘膜中形成的接触孔的蚀刻掩模。 该制造方法包括在层间绝缘膜上形成用作蚀刻掩模的无机膜的步骤; 在无机膜的上部形成用于形成布线槽的第一开口图案的步骤; 以及形成用于形成接触孔的第二开口图案的步骤，以便至少部分地与第一开口图案一致。 此外，通过使用由无机膜制成的蚀刻掩模，在层间绝缘膜中形成接触孔，将无机膜蚀刻到仅形成通过转印第一开口图案而获得的第三开口图案的状态，以及 通过使用所得无机膜作为蚀刻掩模，在层间绝缘膜中形成布线槽。

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