公开(公告)号：US20120032291A1

公开(公告)日：2012-02-09

申请号：US13198458

申请日：2011-08-04

Applicant: Christophe Regnier ,  Olivier Hinsinger ,  Daniel Gloria ,  Pascal Urard

Inventor： Christophe Regnier ,  Olivier Hinsinger ,  Daniel Gloria ,  Pascal Urard

IPC: H01L25/16

CPC classification number: H01L25/16 ,  H01L21/76838 ,  H01L23/481 ,  H01L25/0652 ,  H01L31/02245 ,  H01L2223/6677 ,  H01L2224/16145 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15192 ,  Y02E10/50 ,  H01L2224/81

Abstract: A stand-alone device comprising a silicon wafer having its front surface including a first layer of a first conductivity type and a second layer of a second conductivity type forming a photovoltaic cell; first vias crossing the wafer from the rear surface of the first layer and second vias crossing the wafer from the rear surface of the second layer; metallization levels on the rear surface of the wafer, the external level of these metallization levels defining contact pads; an antenna formed in one of the metallization levels; and one or several chips assembled on said pads; the metallization levels being shaped to provide selected interconnects between the different elements of the device.

Abstract translation: 一种独立装置，包括具有其前表面的硅晶片，该硅晶片包括形成光伏电池的第一导电类型的第一层和第二导电类型的第二层; 从第一层的后表面穿过晶片的第一通孔和从第二层的后表面穿过晶片的第二过孔; 在晶片的后表面上的金属化水平，这些金属化水平的外部水平限定接触垫; 形成在金属化层之一中的天线; 以及组装在所述垫上的一个或多个芯片; 金属化水平被成形为在装置的不同元件之间提供选定的互连。

公开(公告)号：US07853854B2

公开(公告)日：2010-12-14

申请号：US11560316

申请日：2006-11-15

Applicant: Laurent Paumier ,  Pascal Urard ,  Vincent Heinrich

Inventor： Laurent Paumier ,  Pascal Urard ,  Vincent Heinrich

IPC: H03M13/00

CPC classification number: H03M13/1105

Abstract: A method for the iterative decoding of a block of bits having a number N of bits to be decoded where N is a whole number greater than or equal to two, using an iterative decoding algorithm, comprises the generation of a current block of N intermediate decision bits by executing an iteration of the decoding algorithm, followed by the verification of a stability criterion for the current block by comparison of the current block with a given block of N reference bits. If the stability criterion is satisfied, the iterations of the iterative decoding algorithm are stopped and the current block of intermediate decision bits is delivered as a block of hard decision bits. Otherwise another iteration of the decoding algorithm is executed.

Abstract translation: 一种使用迭代解码算法对具有N个大于或等于2的整数的要解码的位数N的位块进行迭代解码的方法包括生成N个中间判决的当前块 通过执行解码算法的迭代，然后通过将当前块与给定的N个参考比特块进行比较来验证当前块的稳定性标准。 如果满足稳定性标准，则停止迭代解码算法的迭代，并将中间判定比特的当前块作为硬判决比特块传送。 否则执行解码算法的另一次迭代。

公开(公告)号：US20080052596A1

公开(公告)日：2008-02-28

申请号：US11834198

申请日：2007-08-06

Applicant: Vincent Heinrich ,  Pascal Urard

Inventor： Vincent Heinrich ,  Pascal Urard

IPC: G06F11/10

CPC classification number: H03M13/1165 ,  H03M13/1105 ,  H03M13/6505 ,  H03M13/6508 ,  H03M13/6566

Abstract: The blocks may be stored temporarily and successively in an input memory before decoding them successively in an iterative manner. The input memory has a memory size allowing the storage of more than two blocks. A current indication representative of a permitted maximum number of iterations for decoding a current block may be defined. The current indication may be initialized to a reference number of iterations increased by an additional number of iterations dependent on the additional memory size of the input memory allowing supplementary storage beyond two blocks. The current block may be decoded until a decoding criterion is satisfied or so long as the number of iterations has not reached the current indication while a first subsequent block and possibly a part of a second subsequent block are stored in the input memory. The current indication may be updated for decoding the first subsequent block as a function of the number of iterations performed for decoding the current block.

Abstract translation: 这些块可以以迭代的方式连续解码之前临时且相继地存储在输入存储器中。 输入存储器具有允许存储多于两个块的存储器大小。 可以定义表示用于解码当前块的允许的最大迭代次数的当前指示。 当前指示可以被初始化为依赖于输入存储器的附加存储器大小的附加数量的迭代增加的参考迭代次数，允许超过两个块的补充存储。 可以解码当前块，直到满足解码标准，或者只要迭代次数尚未达到当前指示，而第一后续块和可能的第二后续块的一部分存储在输入存储器中。 作为对当前块进行解码执行的迭代次数的函数的函数，可以更新当前指示以便解码第一后续块。

公开(公告)号：US20070198896A1

公开(公告)日：2007-08-23

申请号：US11563595

申请日：2006-11-27

Applicant: Laurent Paumier ,  Pascal Urard

Inventor： Laurent Paumier ,  Pascal Urard

IPC: H03M13/00

CPC classification number: H03M13/1105 ,  H03M13/152 ,  H03M13/1555 ,  H03M13/1595 ,  H03M13/2906

Abstract: A concatenated channel decoding method wherein the bits of a set of N1 bits decoded using a first iterative block decoding algorithm and intended to be decoded using a second block decoding algorithm, are sent in parallel in at least one subset of P bits to a buffer for temporary storage. The decoding method comprises receiving in parallel at least one subset of Q bits belonging to the set of N1 bits sent to the buffer, detecting errors with the help of the second decoding algorithm, based on the bits decoded using the first decoding algorithm, and correcting the bits stored in the buffer as a function of possible errors detected. Detecting errors and/or the correcting the stored bits comprise a parallel processing of the bits of each subset of Q bits received.

Abstract translation: 一种级联信道解码方法，其中使用第一迭代块解码算法解码并且想要使用第二块解码算法进行解码的一组N1比特的比特在P比特的至少一个子集中并行发送到缓冲器， 临时存储。 解码方法包括：并行地接收属于发送到缓冲器的N1比特组的Q比特的至少一个子集，借助于第二解码算法检测错误，基于使用第一解码算法解码的比特，以及校正 存储在缓冲器中的位可以作为检测到的可能错误的函数。 检测错误和/或校正所存储的比特包括接收的Q位的每个子集的比特的并行处理。

公开(公告)号：US20070198895A1

公开(公告)日：2007-08-23

申请号：US11560316

申请日：2006-11-15

Applicant: Laurent Paumier ,  Pascal Urard ,  Vincent Heinrich

Inventor： Laurent Paumier ,  Pascal Urard ,  Vincent Heinrich

IPC: H03M13/00

CPC classification number: H03M13/1105

Abstract: A method for the iterative decoding of a block of bits having a number N of bits to be decoded where N is a whole number greater than or equal to two, using an iterative decoding algorithm, comprises the generation of a current block of N intermediate decision bits by executing an iteration of the decoding algorithm, followed by the verification of a stability criterion for the current block by comparison of the current block with a given block of N reference bits. If the stability criterion is satisfied, the iterations of the iterative decoding algorithm are stopped and the current block of intermediate decision bits is delivered as a block of hard decision bits. Otherwise another iteration of the decoding algorithm is executed.

Abstract translation: 一种使用迭代解码算法对具有N个大于或等于2的整数的要解码的位数N的位块进行迭代解码的方法包括生成N个中间判决的当前块 通过执行解码算法的迭代，然后通过将当前块与给定的N个参考比特块进行比较来验证当前块的稳定性标准。 如果满足稳定性标准，则停止迭代解码算法的迭代，并将中间判定比特的当前块作为硬判决比特块传送。 否则执行解码算法的另一次迭代。

公开(公告)号：US07127651B2

公开(公告)日：2006-10-24

申请号：US10914306

申请日：2004-08-09

Applicant: Pascal Urard

Inventor： Pascal Urard

IPC: G01R31/28

CPC classification number: H03H17/0294 ,  H03H17/0621

Abstract: A sampling rate converter includes a chain of identical cells connected in series. An input of a first cell of the chain receives input digital sampling values according to an input frequency. An output of the first cell then delivers output digital sampling values according to an output frequency. The input and output digital sampling values correspond to identical respective reconstruction curves, and the output frequency may be greater than or less than the input frequency. Each cell includes a storage element, two multipliers and two adders.

Abstract translation: 采样率转换器包括串联连接的相同单元的链。 链的第一单元的输入根据输入频率接收输入数字采样值。 然后，第一单元的输出根据输出频率输出输出数字采样值。 输入和输出数字采样值对应于相同的相应重建曲线，并且输出频率可以大于或小于输入频率。 每个单元包括存储元件，两个乘法器和两个加法器。

公开(公告)号：US20050210350A1

公开(公告)日：2005-09-22

申请号：US10914306

申请日：2004-08-09

Applicant: Pascal Urard

Inventor： Pascal Urard

IPC: H03H17/02 ,  H03H17/06 ,  G01R31/28 ,  G06F11/00

CPC classification number: H03H17/0294 ,  H03H17/0621

Abstract: A sampling rate converter includes a chain of identical cells connected in series. An input of a first cell of the chain receives input digital sampling values according to an input frequency. An output of the first cell then delivers output digital sampling values according to an output frequency. The input and output digital sampling values correspond to identical respective reconstruction curves, and the output frequency may be greater than or less than the input frequency. Each cell includes a storage element, two multipliers and two adders.

Abstract translation: 采样率转换器包括串联连接的相同单元的链。 链的第一单元的输入根据输入频率接收输入数字采样值。 然后，第一单元的输出根据输出频率输出输出数字采样值。 输入和输出数字采样值对应于相同的相应重建曲线，并且输出频率可以大于或小于输入频率。 每个单元包括存储元件，两个乘法器和两个加法器。

公开(公告)号：US08499228B2

公开(公告)日：2013-07-30

申请号：US12914306

申请日：2010-10-28

Applicant: Vincent Heinrich ,  Pascal Urard

Inventor： Vincent Heinrich ,  Pascal Urard

IPC: H03M13/03

CPC classification number: G11B20/1803 ,  G11B2020/10759 ,  H03M13/1111 ,  H03M13/2957 ,  H03M13/3972 ,  H03M13/4146 ,  H03M13/6343 ,  H03M13/6502

Abstract: A method is for decoding a block of N information items encoded with an error correction code and mutually correlated. The method includes carrying out a first decorrelation of the N information items of a block is carried out, and storing the block decorrelated. The method also includes a performing a processing for decoding a group of P information items of the block, and decorrelating at least part of the P decoded information items. The processing for decoding the group of P information items and the decorrelation are repeated with different successive groups of P information items of the block until the N information items of the block have been processed, until a decoding criterion is satisfied.

Abstract translation: 一种方法是解码用纠错码编码并相互相关的N个信息项的块。 该方法包括执行块的N个信息项的第一去相关，并且存储相关的块。 该方法还包括执行用于解码该块的P个信息项的处理，以及对至少部分的P个解码的信息项进行解相关。 用于解码P个信息项的组合和解相关的处理被重复，直到块的N个信息项已经被处理之前的不同的连续的P个信息项组，直到满足解码标准。

公开(公告)号：US20120173947A1

公开(公告)日：2012-07-05

申请号：US12676802

申请日：2008-09-02

Applicant: Adrian Voicila ,  David Declercq ,  Marc Fossorier ,  François Verdier ,  Pascal Urard

Inventor： Adrian Voicila ,  David Declercq ,  Marc Fossorier ,  François Verdier ,  Pascal Urard

IPC: H03M13/05 ,  G06F11/10

CPC classification number: H03M13/1171 ,  H03M13/1134 ,  H03M13/114 ,  H03M13/116 ,  H03M13/118 ,  H03M13/6502

Abstract: A string of K initial symbols is encoded with a code of the parity check type. The K initial symbols belong to a Galois field of order q strictly greater than 2. The code is defined by code characteristics representable by a graph (GRH) comprising N−K first nodes (NCi), each node satisfying a parity check equation defined on the Galois field of order q, N packets of intermediate nodes (NITi) and NI second nodes (NSSi), each intermediate node being linked to a single first node and to several second nodes by way of a connection scheme. The string of K initial symbols is encoded by using the said code characteristics and a string of N encoded symbols is obtained, respectively subdivided into NI sub-symbols belonging respectively to mathematical sets whose orders are less than q, according to a subdivision scheme representative of the connection scheme (H).

Abstract translation: 一组K个初始符号用奇偶校验类型的代码编码。 K个初始符号属于严格大于2的阶数q的Galois域。该码由包含N-K个第一节点（NCi）的图形（GRH）表示的代码特征定义，每个节点满足在 阶次q的伽罗瓦域，中间节点（NITi）和NI第二节点（NSSi）的N个分组，每个中间节点通过连接方案链接到单个第一节点和多个第二节点。 通过使用所述代码特征对K个初始符号的串进行编码，并且获得一组N个编码符号，分别被分为归属于小于q的数学集的NI子符号，根据代表 连接方案（H）。

公开(公告)号：US07966544B2

公开(公告)日：2011-06-21

申请号：US11737442

申请日：2007-04-19

Applicant: Laurent Paumier ,  Pascal Urard

Inventor： Laurent Paumier ,  Pascal Urard

IPC: H03M13/00

CPC classification number: H03M13/1165 ,  H03M13/1105 ,  H03M13/1134 ,  H03M13/1137 ,  H03M13/27 ,  H03M13/2757 ,  H03M13/2792

Abstract: An input memory of an LDPC decoder is loaded with data corresponding to an LDPC frame to be decoded and including N LLRs, of which K are information LLRs and N−K are parity LLRs. At least one stream is formed of binary words of a first type, each corresponding to multiple information LLRS, with the aid of a serial/parallel conversion module, and at least one stream is formed of binary words of a second type, each corresponding to multiple parity LLRs, with the aid of a row/column interlacing device comprising a two-dimensional first-in first-out ring buffer. The first memory accesses are made in page mode in order to write the binary words of the first type to a first zone of the input memory, and the second memory accesses are made in page mode in order to write the binary words of the second type to a second zone.

Abstract translation: LDPC解码器的输入存储器加载与要解码的LDPC帧相对应的数据，并且包括N个LLR，其中K是信息LLR，N-K是奇偶校验LLR。 借助于串行/并行转换模块，至少一个流由第二类型的二进制字形成，每个二进制字对应于多个信息LLRS，并且至少一个流由第二类型的二进制字形成，每一个对应于 借助于包括二维先进先出环形缓冲器的行/列交织装置的多个奇偶校验LLR。 第一存储器访问是以页模式进行的，以便将第一类型的二进制字写入输入存储器的第一区，并且第二存储器访问以页模式进行，以便写入第二类的二进制字 到第二区。