Abstract:
The present invention relates to electronic memory circuits, and more particularly, to low power electronic memory circuits having low manufacturing costs. The present invention is a circuit design that utilizes two transistor types—bipolar and MOS (but, not both NMOS and PMOS) one of which can be manufactured together with the memory cell's non-linear conductive elements (such as a diode) thereby reducing the number of processing steps and masks and resulting in lower cost.
Abstract:
A method and system of communicating between a wireless network and a process control system communicatively coupled to a server, such as OPC. The server receives data from the wireless network, where the data is generated from an input/output data point within the wireless network. The server maps the data between the input/output data point and a data point placeholder within the process control system. The server writes the mapped data to the corresponding data point placeholder of the process control system via a process control interface, and the mapped data is provided to the process control system as process control data native to the process control system. Process control data may also be provided to the server, mapped between a data point placeholder of the process control system and an input/output data point of the wireless network, and written to the corresponding input/output data point.
Abstract:
An electronic circuit such as a latch or a sequencer includes a plurality of transistors, all of the transistors being either NMOS transistors or PMOS transistors, and dissipates less than or approximately the same amount of power as an equivalent CMOS circuit.
Abstract:
A high-density memory device is fabricated three-dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers.
Abstract:
The invention concerns in one embodiment a method for treating glaucoma or elevated IOP in a patient comprising administering to the patient an effective amount of a composition comprising an agent that inhibits PAI-1 expression or PAI-1 activity. Another embodiment of the present invention is a method of treating a PAI-1-associated ocular disorder in a subject in need, comprising administering to the patient an effective amount of a composition comprising an agent that inhibits PAI-1 activity or expression.
Abstract:
A high-density memory device is fabricated three-dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers.
Abstract:
In various embodiments, an addressable storage matrix includes a first plurality of intersection points, at least some of which are bridged by two-terminal non-linear elements that exhibit a threshold below which current flow is significantly lower than if the threshold is exceeded, as well as, disposed at each intersection point bridged by a non-linear element, a programmable material in series with the non-linear element and determining a bit state for the corresponding intersection point.
Abstract:
RNA interference is provided for inhibition of connective tissue growth factor mRNA expression in ocular disorders involving CTGF expression. Ocular disorders involving aberrant CTGF expression include glaucoma, macular degeneration, diabetic retinopathy, choroidal neovascularization, proliferative vitreoretinopathy and wound healing. Such disorders are treated by administering interfering RNAs of the present invention.
Abstract:
RNA interference is provided for inhibition of connective tissue growth factor mRNA expression in ocular disorders involving CTGF expression. Ocular disorders involving aberrant CTGF expression include glaucoma, macular degeneration, diabetic retinopathy, choroidal neovascularization, proliferative vitreoretinopathy and wound healing. Such disorders are treated by administering interfering RNAs of the present invention.
Abstract:
A high density memory device is fabricated three dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers.