公开(公告)号：US08455306B2

公开(公告)日：2013-06-04

申请号：US13480924

申请日：2012-05-25

申请人： Amaury Gendron ,  Chai Ean Gill ,  Rouying Zhan

发明人： Amaury Gendron ,  Chai Ean Gill ,  Rouying Zhan

IPC分类号： H01L21/332 ,  H01L21/00 ,  H01L27/02

CPC分类号： H01L21/00 ,  H01L27/0259 ,  H01L27/0262 ,  H01L29/0649 ,  H01L29/66121 ,  H01L29/87

摘要： Embodiments include methods for forming an electrostatic discharge (ESD) protection device coupled across input-output (I/O) and common terminals of a core circuit, where the ESD protection device includes first and second merged bipolar transistors. A base of the first transistor serves as collector of the second transistor and the base of the second transistor serves as collector of the first transistor, the bases having, respectively, first and second widths. A first resistance is coupled between an emitter and base of the first transistor and a second resistance is coupled between an emitter and base of the second transistor. ESD trigger voltage Vt1 and holding voltage Vh can be independently optimized by choosing appropriate base widths and resistances. By increasing Vh to approximately equal Vt1, the ESD protection is more robust, especially for applications with narrow design windows, for example, with operating voltage close to the degradation voltage.

摘要翻译： 实施例包括用于形成耦合在输入输出（I / O）和核心电路的公共端子之间的静电放电（ESD）保护装置的方法，其中ESD保护装置包括第一和第二合并双极晶体管。 第一晶体管的基极用作第二晶体管的集电极，第二晶体管的基极用作第一晶体管的集电极，基极分别具有第一和第二宽度。 第一电阻耦合在第一晶体管的发射极和基极之间，第二电阻耦合在第二晶体管的发射极和基极之间。 ESD触发电压Vt1和保持电压Vh可以通过选择合适的基极宽度和电阻来独立优化。 通过将Vh增加到大致相等的Vt1，ESD保护更稳健，特别是对于具有窄设计窗口的应用，例如，工作电压接近劣化电压。

公开(公告)号：US20120295414A1

公开(公告)日：2012-11-22

申请号：US13561990

申请日：2012-07-30

申请人： Rouying Zhan ,  Amaury Gendron ,  Chai Ean Gill

发明人： Rouying Zhan ,  Amaury Gendron ,  Chai Ean Gill

IPC分类号： H01L21/76 ,  H01L21/8222

CPC分类号： H01L27/0259

摘要： Methods are provided for producing stacked electrostatic discharge (ESD) clamps. In one embodiment, the method includes providing a semiconductor substrate in which first and second serially-coupled transistors are formed. The first transistor includes a first well region having a first lateral edge partially forming the first transistor's base. The second transistor including a second well region having a second lateral edge partially forming the second transistor's base. Third and fourth well regions are formed in the first and second transistors, respectively, and extend a different distance into the substrate than do the well regions of the first and second transistors. The third well region has a third lateral edge separated from the first lateral edge by a first spacing dimension D1. The fourth well region has a fourth lateral edge separated from the second lateral edge by a second spacing dimension D2, which is different than D1.

摘要翻译： 提供了用于生产叠层静电放电（ESD）夹具的方法。 在一个实施例中，该方法包括提供形成第一和第二串联耦合晶体管的半导体衬底。 第一晶体管包括具有部分地形成第一晶体管的基极的第一侧边缘的第一阱区。 第二晶体管包括具有部分地形成第二晶体管的基极的第二横向边缘的第二阱区。 第三和第四阱区分别形成在第一和第二晶体管中，并且与第一和第二晶体管的阱区相比，延伸到衬底中的不同距离。 第三阱区域具有与第一侧边缘分开第一间隔尺寸D1的第三横向边缘。 第四阱区具有与第二侧边缘分离第二间隔尺寸D2的第四横向边缘，其不同于D1。

公开(公告)号：US09177952B2

公开(公告)日：2015-11-03

申请号：US14053716

申请日：2013-10-15

申请人： Rouying Zhan ,  Chai Ean Gill ,  Changsoo Hong ,  Michael H. Kaneshiro

发明人： Rouying Zhan ,  Chai Ean Gill ,  Changsoo Hong ,  Michael H. Kaneshiro

IPC分类号： H01L29/74 ,  H01L29/747 ,  H01L29/00 ,  H01L21/331 ,  H01L27/082 ,  H01L29/73 ,  H01L27/02 ,  H01L29/66 ,  H01L23/60

CPC分类号： H01L27/0259 ,  H01L23/60 ,  H01L27/0248 ,  H01L27/0262 ,  H01L27/082 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/66234 ,  H01L29/6625 ,  H01L29/73 ,  H01L29/7317 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrostatic discharge (ESD) protection device includes a semiconductor substrate comprising a buried insulator layer and a semiconductor layer over the buried insulator layer having a first conductivity type, and first and second bipolar transistor devices disposed in the semiconductor layer, laterally spaced from one another, and sharing a common collector region having a second conductivity type. The first and second bipolar transistor devices are configured in an asymmetrical arrangement in which the second bipolar transistor device includes a buried doped layer having the second conductivity type and extending along the buried insulator layer from the common collector region across a device area of the second bipolar transistor device.

摘要翻译： 静电放电（ESD）保护装置包括半导体衬底，该半导体衬底包括掩埋绝缘体层和在具有第一导电类型的掩埋绝缘体层上的半导体层，以及设置在半导体层中的彼此横向间隔开的第一和第二双极晶体管器件 并且共享具有第二导电类型的公共收集器区域。 第一和第二双极晶体管器件被配置成非对称布置，其中第二双极晶体管器件包括具有第二导电类型的掩埋掺杂层，并且沿着埋在绝缘体层的跨第二极二极管的器件区域的公共集电极区域延伸 晶体管器件。

公开(公告)号：US20140347771A1

公开(公告)日：2014-11-27

申请号：US13900226

申请日：2013-05-22

申请人： Rouying ZHAN ,  Chai Ean GILL ,  Wen-Yi CHEN ,  Michael H. KANESHIRO

发明人： Rouying ZHAN ,  Chai Ean GILL ,  Wen-Yi CHEN ,  Michael H. KANESHIRO

IPC分类号： H01L29/74 ,  H02H9/04 ,  H01L29/66

CPC分类号： H02H9/044 ,  H01L27/0259 ,  H01L29/7322 ,  H02H9/046

摘要： Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a first base region of semiconductor material having a first conductivity type, a second base region of semiconductor material having the first conductivity type and a dopant concentration that is less than the first base region, a third base region of semiconductor material having the first conductivity type and a dopant concentration that is greater than the second base region, an emitter region of semiconductor material having a second conductivity type opposite the first conductivity type within the first base region, and a collector region of semiconductor material having the second conductivity type. At least a portion of the second base region resides between the third base region and the first base region and at least a portion of the first base region resides between the emitter region and the collector region.

摘要翻译： 提供了保护装置结构和相关制造方法。 一种示例性的半导体保护装置包括具有第一导电类型的半导体材料的第一基极区域，具有第一导电类型的第二基极区域和具有小于第一基极区域的掺杂剂浓度的第二基极区域，半导体的第三基极区域 具有第一导电类型和大于第二基极区的掺杂剂浓度的材料，具有与第一基极区内的第一导电类型相反的第二导电类型的半导体材料的发射极区域和具有第一导电类型的半导体材料的集电极区域， 第二导电类型。 第二基极区域的至少一部分位于第三基极区域和第一基极区域之间，并且第一基极区域的至少一部分位于发射极区域和集电极区域之间。

公开(公告)号：US20140346560A1

公开(公告)日：2014-11-27

申请号：US13900256

申请日：2013-05-22

申请人： Rouying ZHAN ,  Chai Ean GILL ,  Wen-Yi CHEN ,  Michael H. KANESHIRO

发明人： Rouying ZHAN ,  Chai Ean GILL ,  Wen-Yi CHEN ,  Michael H. KANESHIRO

IPC分类号： H01L29/74 ,  H01L29/66

CPC分类号： H01L27/0259

摘要： Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a base well region having a first conductivity type, an emitter region within the base well region having a second conductivity type opposite the first conductivity type, a collector region having the second conductivity type, a first floating region having the second conductivity type within the base well region between the emitter region and the collector region, and a second floating region having the first conductivity type within the base well region between the first floating region and the collector region. The floating regions within the base well region are electrically connected to reduce current gain and improve holding voltage.

摘要翻译： 提供了保护装置结构和相关制造方法。 示例性的半导体保护装置包括具有第一导电类型的基极阱区域，在基极阱区域内的发射极区域具有与第一导电类型相反的第二导电类型，具有第二导电类型的集电极区域，具有第二导电类型的第一浮动区域， 在发射极区域和集电极区域之间的基极阱区域内的第二导电类型，以及在第一浮动区域和集电极区域之间的基极阱区域内具有第一导电类型的第二浮动区域。 基极区域内的浮动区域电连接以减小电流增益并改善保持电压。

公开(公告)号：US20140235026A1

公开(公告)日：2014-08-21

申请号：US14168807

申请日：2014-01-30

申请人： ROUYING ZHAN ,  AMAURY GENDRON ,  CHAI EAN GILL

发明人： ROUYING ZHAN ,  AMAURY GENDRON ,  CHAI EAN GILL

IPC分类号： H01L21/8228

CPC分类号： H01L21/8228 ,  H01L27/0259 ,  H01L29/66234

摘要： Methods for forming an electrostatic discharge protection (ESD) clamps are provided. In one embodiment, the method includes forming at least one transistor having a first well region of a first conductivity type extending into a substrate. At least one transistor is formed having another well region of a second opposite conductivity type, which extends into the substrate to partially form a collector. The lateral edges of the transistor well regions are separated by a distance D, which at least partially determines a threshold voltage Vt1 of the ESD clamp. A base contact of the first conductivity type is formed in the first well region and separated from an emitter of the second conductivity type by a lateral distance Lbe. The first doping density and the lateral distance Lbe are selected to provide a parasitic base-emitter resistance Rbe in the range of 1

摘要翻译： 提供了形成静电放电保护（ESD）夹具的方法。 在一个实施例中，该方法包括形成至少一个具有延伸到衬底中的第一导电类型的第一阱区的晶体管。 至少一个晶体管形成有具有第二相反导电类型的另一阱区，其延伸到衬底中以部分地形成集电极。 晶体管阱区的横向边缘被隔开距离D，距离D至少部分地确定ESD钳位的阈值电压Vt1。 第一导电类型的基极接触形成在第一阱区中，并且与第二导电类型的发射极分开横向距离Lbe。 选择第一掺杂浓度和横向距离Lbe以在1

公开(公告)号：US20140061716A1

公开(公告)日：2014-03-06

申请号：US13599244

申请日：2012-08-30

申请人： Rouying Zhan ,  Chai Ean c. Gill ,  Changsoo Hong

发明人： Rouying Zhan ,  Chai Ean c. Gill ,  Changsoo Hong

IPC分类号： H01L29/747 ,  H01L21/332

CPC分类号： H01L29/87 ,  H01L27/0262

摘要： An electrostatic discharge protection clamp adapted to limit a voltage appearing across protected terminals of an integrated circuit to which the electrostatic discharge protection clamp is coupled is presented. The electrostatic discharge protection clamp includes a substrate, and a first electrostatic discharge protection device formed over the substrate. The first electrostatic discharge protection device includes a buried layer formed over the substrate, the buried layer having a first conductivity type and defining an opening located over a region of the substrate, a first transistor formed over the opening of the buried layer, the first transistor having an emitter coupled to a first cathode terminal of the electrostatic discharge protection clamp, and a second transistor formed over the buried layer, the second transistor having an emitter coupled to a first anode terminal of the electrostatic discharge protection clamp

摘要翻译： 本发明提供了一种静电放电保护钳，其适用于限制出现在静电放电保护钳耦合到的集成电路的受保护端子上的电压。 静电放电保护夹具包括衬底和形成在衬底上的第一静电放电保护器件。 第一静电放电保护器件包括形成在衬底上的掩埋层，所述掩埋层具有第一导电类型并且限定位于衬底的区域上方的开口，形成在掩埋层的开口上的第一晶体管，第一晶体管 具有耦合到所述静电放电保护钳位件的第一阴极端子的发射极和形成在所述掩埋层上的第二晶体管，所述第二晶体管具有耦合到所述静电放电保护钳位件的第一阳极端子的发射极

公开(公告)号：US08432654B2

公开(公告)日：2013-04-30

申请号：US13612466

申请日：2012-09-12

申请人： James D. Whitfield ,  Chai Ean Gill ,  Abhijat Goyal ,  Rouying Zhan

发明人： James D. Whitfield ,  Chai Ean Gill ,  Abhijat Goyal ,  Rouying Zhan

IPC分类号： H02H9/00

CPC分类号： H01L27/0248

摘要： An electrostatic discharge (ESD) clamp, coupled across input-output (I/O) and common (GND) terminals of a protected semiconductor device or integrated circuit is provided. One ESD clamp comprises an ESD transistor (ESDT) with source-drain coupled between the GND and I/O terminals, a first resistor coupled between the gate and source and a second resistor coupled between the ESDT body and source. Paralleling the resistors are control transistors with gates coupled to one or more bias supplies Vb, Vb′. The main power rail (Vdd) of the device or IC is a convenient source for Vb, Vb′. When the Vdd is off during shipment, handling, equipment assembly, etc., the ESD trigger voltage Vt1 is low, thereby providing maximum ESD protection when ESD risk is high. When Vdd is energized, Vt1 rises to a value large enough to avoid interference with normal circuit operation but still protect from ESD events.

摘要翻译： 提供了耦合在受保护的半导体器件或集成电路的输入输出（I / O）和公共（GND）端子之间的静电放电（ESD）钳位。 一个ESD钳位包括源极 - 漏极耦合在GND和I / O端子之间的ESD晶体管（ESDT），耦合在栅极和源极之间的第一个电阻器和耦合在ESDT体和源极之间的第二个电阻器。 并联电阻器是控制晶体管，其栅极耦合到一个或多个偏置电源Vb，Vb'。 设备或IC的主电源轨（Vdd）是Vb，Vb'的方便源。 当Vdd在装运，处理，设备组装等时关闭时，ESD触发电压Vt1为低，从而在ESD风险高时提供最大的ESD保护。 当Vdd通电时，Vt1上升到足够大的值，以避免与正常电路操作的干扰，但仍然保护ESD事件。

公开(公告)号：US08390092B2

公开(公告)日：2013-03-05

申请号：US12944931

申请日：2010-11-12

申请人： Amaury Gendron ,  Chai Ean Gill ,  Vadim A. Kushner ,  Rouying Zhan

发明人： Amaury Gendron ,  Chai Ean Gill ,  Vadim A. Kushner ,  Rouying Zhan

IPC分类号： H01L23/58

CPC分类号： H01L27/0262 ,  H01L29/87

摘要： An area-efficient, high voltage, single polarity ESD protection device (300) is provided which includes an p-type substrate (303); a first p-well (308-1) formed in the substrate and sized to contain n+ and p+ contact regions (310, 312) that are connected to a cathode terminal; a second, separate p-well (308-2) formed in the substrate and sized to contain only a p+ contact region (311) that is connected to an anode terminal; and an electrically floating n-type isolation structure (304, 306, 307-2) formed in the substrate to surround and separate the first and second semiconductor regions. When a positive voltage exceeding a triggering voltage level is applied to the cathode and anode terminals, the ESD protection device triggers an inherent thyristor into a snap-back mode to provide a low impedance path through the structure for discharging the ESD current.

公开(公告)号：US20120231587A1

公开(公告)日：2012-09-13

申请号：US13480924

申请日：2012-05-25

申请人： AMAURY GENDRON ,  Chai Ean Gill ,  Rouying Zhan

发明人： AMAURY GENDRON ,  Chai Ean Gill ,  Rouying Zhan

IPC分类号： H01L21/33

CPC分类号： H01L21/00 ,  H01L27/0259 ,  H01L27/0262 ,  H01L29/0649 ,  H01L29/66121 ,  H01L29/87

摘要： Embodiments include methods for forming an electrostatic discharge (ESD) protection device coupled across input-output (I/O) and common terminals of a core circuit, where the ESD protection device includes first and second merged bipolar transistors. A base of the first transistor serves as collector of the second transistor and the base of the second transistor serves as collector of the first transistor, the bases having, respectively, first and second widths. A first resistance is coupled between an emitter and base of the first transistor and a second resistance is coupled between an emitter and base of the second transistor. ESD trigger voltage Vt1 and holding voltage Vh can be independently optimized by choosing appropriate base widths and resistances. By increasing Vh to approximately equal Vt1, the ESD protection is more robust, especially for applications with narrow design windows, for example, with operating voltage close to the degradation voltage.

摘要翻译： 实施例包括用于形成耦合在输入输出（I / O）和核心电路的公共端子之间的静电放电（ESD）保护装置的方法，其中ESD保护装置包括第一和第二合并双极晶体管。 第一晶体管的基极用作第二晶体管的集电极，第二晶体管的基极用作第一晶体管的集电极，基极分别具有第一和第二宽度。 第一电阻耦合在第一晶体管的发射极和基极之间，第二电阻耦合在第二晶体管的发射极和基极之间。 ESD触发电压Vt1和保持电压Vh可以通过选择合适的基极宽度和电阻来独立优化。 通过将Vh增加到大致相等的Vt1，ESD保护更稳健，特别是对于具有窄设计窗口的应用，例如，工作电压接近劣化电压。