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公开(公告)号：US20140192715A1
公开(公告)日：2014-07-10
申请号：US13993346
申请日：2011-12-30
Applicant: Omesh Tickoo , Ravishankar Iyer
Inventor： Omesh Tickoo , Ravishankar Iyer
Abstract: A route for establishing a wireless connection between a wireless device and a node may be selected based on an estimated duration of the route. The route duration may be estimated based on information related to the expected movement of nodes included in the route.
Abstract translation: 可以基于路由的估计持续时间来选择用于在无线设备和节点之间建立无线连接的路由。 可以基于与路由中包括的节点的预期移动相关的信息来估计路由持续时间。
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公开(公告)号：US20140115259A1
公开(公告)日：2014-04-24
申请号：US14141992
申请日：2013-12-27
Applicant: Andrew Herdrich , Ramesh Illikkal , Donald Newell , Ravishankar Iyer , Vineet Chadha
Inventor： Andrew Herdrich , Ramesh Illikkal , Donald Newell , Ravishankar Iyer , Vineet Chadha
CPC classification number: G06F9/44505 , G06F1/10 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F9/50 , G06F9/5094 , G06F12/0891 , Y02D10/128
Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.
Abstract translation: 一种装置包括多个核心和耦合到核心的控制器。 如果基于与第二核心相关联的每个指令（CPI）的处理器时钟周期的第一数量高于第一阈值，则控制器将降低第一核心的工作点。 如果第一数量低于第二阈值，则控制器可操作以增加第一核心的工作点。
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公开(公告)号：US20140095794A1
公开(公告)日：2014-04-03
申请号：US13631625
申请日：2012-09-28
Applicant: Jaideep MOSES , Ravishankar IYER , Ramesh G. ILLIKKAL , Sadagopan SRINIVASAN
Inventor： Jaideep MOSES , Ravishankar IYER , Ramesh G. ILLIKKAL , Sadagopan SRINIVASAN
IPC: G06F12/08
CPC classification number: G06F12/08 , G06F12/0891
Abstract: A processor is described having cache circuitry and logic circuitry. The logic circuitry is to manage the entry and removal of cache lines from the cache circuitry. The logic circuitry includes storage circuitry and control circuitry. The storage circuitry is to store information identifying a set of cache lines within the cache that are in a modified state. The control circuitry is coupled to the storage circuitry to receive the information from the storage circuitry, responsive to a signal to flush the cache, and determine addresses of the cache therefrom so that the set of cache lines are read from the cache so as to avoid reading cache lines from the cache that are in an invalid or a clean state.
Abstract translation: 描述了具有高速缓存电路和逻辑电路的处理器。 逻辑电路是管理高速缓存线路的高速缓存行的输入和移除。 逻辑电路包括存储电路和控制电路。 存储电路用于存储标识高速缓存中处于修改状态的一组高速缓存行的信息。 控制电路耦合到存储电路，以响应于刷新高速缓存的信号从存储电路接收信息，并从其中确定高速缓存的地址，从而从高速缓存读取高速缓存行集合，以避免 从缓存中读取处于无效或干净状态的缓存行。
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公开(公告)号：US08412885B2
公开(公告)日：2013-04-02
申请号：US12590651
申请日：2009-11-12
Applicant: Liqun Cheng , Zhen Fang , Jeffrey Wilder , Sadagopan Srinivasan , Ravishankar Iyer , Donald Newell
Inventor： Liqun Cheng , Zhen Fang , Jeffrey Wilder , Sadagopan Srinivasan , Ravishankar Iyer , Donald Newell
IPC: G06F12/00
CPC classification number: G06F12/0895 , Y02D10/13
Abstract: In an embodiment of the present invention a method includes: sending request for data to a memory controller; arranging the request for data by order of importance or priority; identifying a source of the request for data; and if the source is an input/output device, masking off P ways in a cache; and allocating ways in filling the cache. Other embodiments are described and claimed.
Abstract translation: 在本发明的实施例中，一种方法包括：向存储器控制器发送数据请求; 按重要性或优先次序安排数据请求; 识别数据请求的来源; 并且如果源是输入/输出设备，则遮蔽高速缓存中的P路; 并分配填充缓存的方法。 描述和要求保护其他实施例。
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公开(公告)号：US08225069B2
公开(公告)日：2012-07-17
申请号：US12415941
申请日：2009-03-31
Applicant: Zhen Fang , Mahesh Wagh , Jasmin Ajanovic , Michael E Espig , Ravishankar Iyer
Inventor： Zhen Fang , Mahesh Wagh , Jasmin Ajanovic , Michael E Espig , Ravishankar Iyer
IPC: G06F12/00
CPC classification number: G06F12/1036 , G06F12/0292 , G06F12/0888 , G06F12/10 , G06F12/1027 , G06F2212/206
Abstract: Methods and apparatus for control of On-Die System Fabric (OSF) blocks are described. In one embodiment, a shadow address corresponding to a physical address may be stored in response to a user-level request and a logic circuitry (e.g., present in an OSF) may determine the physical address from the shadow address. Other embodiments are also disclosed.
Abstract translation: 描述了用于控制片上系统结构（OSF）块的方法和装置。 在一个实施例中，响应于用户级请求可以存储对应于物理地址的影子地址，并且逻辑电路（例如，存在于OSF中）可以从影子地址确定物理地址。 还公开了其他实施例。
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Patent Agency Ranking
公开(公告)号：US20120082387A1
公开(公告)日：2012-04-05
申请号：US12896077
申请日：2010-10-01
Applicant: Yong Zhang , Ravishankar Iyer , Rameshkumar G. Illikkal , Donald K. Newell , Jianping Zhou
Inventor： Yong Zhang , Ravishankar Iyer , Rameshkumar G. Illikkal , Donald K. Newell , Jianping Zhou
IPC: G06K9/46
CPC classification number: G06K9/481 , G06K9/00973 , G06K9/4671 , G06K2009/485
Abstract: Methods and systems of recognizing images may include an apparatus having a hardware module with logic to, for a plurality of vectors in an image, determine a first intermediate computation based on even pixels of an image vector, and determine a second intermediate computation based on odd pixels of an image vector. The logic can also combine the first and second intermediate computations into a Hessian matrix computation.
Abstract translation: 识别图像的方法和系统可以包括具有硬件模块的装置，该硬件模块具有对于图像中的多个向量的逻辑，基于图像矢量的偶数像素确定第一中间计算，并且基于奇数来确定第二中间计算 图像矢量的像素。 逻辑还可以将第一和第二中间计算组合成Hessian矩阵计算。
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公开(公告)号：US20110161595A1
公开(公告)日：2011-06-30
申请号：US12647461
申请日：2009-12-26
Applicant: Zhen Fang , Meenakshisundara R. Chinthamani , Li Zhao , Milind B. Kamble , Ravishankar Iyer , Seung Eun Lee , Robert S. Chappell , Ryan L. Carlson
Inventor： Zhen Fang , Meenakshisundara R. Chinthamani , Li Zhao , Milind B. Kamble , Ravishankar Iyer , Seung Eun Lee , Robert S. Chappell , Ryan L. Carlson
CPC classification number: G06F12/0864 , G06F1/3225 , G06F1/3275 , G06F12/0895 , G06F2212/1028 , Y02D10/13 , Y02D10/14
Abstract: Methods and apparatus to provide for power consumption reduction in memories (such as cache memories) are described. In one embodiment, a virtual tag is used to determine whether to access a cache way. The virtual tag access and comparison may be performed earlier in the read pipeline than the actual tag access or comparison. In another embodiment, a speculative way hit may be used based on pre-ECC partial tag match to wake up a subset of data arrays. Other embodiments are also described.
Abstract translation: 描述了提供存储器（诸如高速缓存存储器）中的功耗降低的方法和装置。 在一个实施例中，使用虚拟标签来确定是否访问缓存方式。 虚拟标签访问和比较可以在读取管道中比实际标签访问或比较更早地进行。 在另一个实施例中，可以基于ECC前部分标签匹配来使用推测方式命中来唤醒数据阵列的子集。 还描述了其它实施例。
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公开(公告)号：US20110113198A1
公开(公告)日：2011-05-12
申请号：US12590651
申请日：2009-11-12
Applicant: Liqun Cheng , Zhen Fang , Jeffrey Wilder , Sadagopan Srinivasan , Ravishankar Iyer , Donald Newell
Inventor： Liqun Cheng , Zhen Fang , Jeffrey Wilder , Sadagopan Srinivasan , Ravishankar Iyer , Donald Newell
CPC classification number: G06F12/0895 , Y02D10/13
Abstract: The present invention discloses a method comprising: sending request for data to a memory controller; arranging the request for data by order of importance or priority; identifying a source of the request for data; if the source is an input/output device, masking off P ways in a cache; and allocating ways in filling the cache. The method further includes extending cache allocation logic to control a tag comparison operation by using a bit to provide a hint from IO devices that certain ways will not have requested data.
Abstract translation: 本发明公开了一种方法，包括：向存储器控制器发送数据请求; 按重要性或优先次序安排数据请求; 识别数据请求的来源; 如果源是输入/输出设备，则屏蔽高速缓存中的P路; 并分配填充缓存的方法。 该方法还包括扩展高速缓存分配逻辑以通过使用位来提供来自IO设备的某些方式将不会请求数据的提示来控制标签比较操作。
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公开(公告)号：US20110087843A1
公开(公告)日：2011-04-14
申请号：US12587670
申请日：2009-10-09
Applicant: Li Zhao , Ravishankar Iyer , Rameshkumar G. Illikkal , Erik G. Hallnor , Martin G. Dixon , Donald K. Newell
Inventor： Li Zhao , Ravishankar Iyer , Rameshkumar G. Illikkal , Erik G. Hallnor , Martin G. Dixon , Donald K. Newell
CPC classification number: G06F12/0864
Abstract: An apparatus, method, and system are disclosed. In one embodiment the apparatus includes a cache memory, which a number of sets. Each of the sets in the cache memory have several cache lines. The apparatus also includes at least one process resource table. The process resource table maintains a cache line occupancy count of a number of cache lines. Specifically, the cache line occupancy count for each cache line describes the number of cache lines in the cache storing information utilized by a process running on a computer system. Additionally, the process resource table stores the occupancy count of less cache lines than the total number of cache lines in the cache memory.
Abstract translation: 公开了一种装置，方法和系统。 在一个实施例中，该装置包括多个组的高速缓冲存储器。 高速缓冲存储器中的每个集合具有多个高速缓存行。 该装置还包括至少一个进程资源表。 进程资源表维护多个高速缓存行的高速缓存行占用数。 具体地说，每个高速缓存行的高速缓存线占用率表示高速缓存存储由计算机系统上运行的进程使用的信息的高速缓存行数。 此外，处理资源表存储比高速缓冲存储器中的高速缓存行总数少的高速缓存行的占用数。
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公开(公告)号：US20100250998A1
公开(公告)日：2010-09-30
申请号：US12414504
申请日：2009-03-30
Applicant: Andrew Herdrich , Ramesh Illikkal , Donald Newell , Ravishankar Iyer , Vineet Chadha
Inventor： Andrew Herdrich , Ramesh Illikkal , Donald Newell , Ravishankar Iyer , Vineet Chadha
IPC: G06F1/08
CPC classification number: G06F9/44505 , G06F1/10 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F9/50 , G06F9/5094 , G06F12/0891 , Y02D10/128
Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.
Abstract translation: 一种装置包括多个核心和耦合到核心的控制器。 如果基于与第二核心相关联的每个指令（CPI）的处理器时钟周期的第一数量高于第一阈值，则控制器将降低第一核心的工作点。 如果第一数量低于第二阈值，则控制器可操作以增加第一核心的工作点。
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