公开(公告)号：US4739499A

公开(公告)日：1988-04-19

申请号：US838495

申请日：1986-03-11

Applicant: Richard D. Simpson

Inventor： Richard D. Simpson

IPC: G11C11/41 ,  G11C7/06 ,  G11C11/417 ,  G11C11/419 ,  H03K3/356 ,  G11C7/00

CPC classification number: G11C7/065 ,  H03K3/356104

Abstract: A CMOS random access memory has storage elements (1, 2 and 3) which produce complementary outputs on a pair of output conductors (7, 8). In order to speed up the establishment of the output voltages on the conductors two cross-connected transistors (22, 23) are provided to supplement the discharging of that conductor which is to have the lower voltage, each transistor being responsive to the voltage on one conductor to discharge the other conductor. The correct timing of the operation of the cross-connected transistors is provided by two further transistors (26, 27) having their gates respectively connected to the conductors which are arranged to become conducting when an adequate voltage charge has been achieved by the storage element. When either of the further transistors conducts a transistor (24) in series with the two cross-connected transistors is turned on to enable them to operate.

Abstract translation: CMOS随机存取存储器具有在一对输出导体（7,8）上产生互补输出的存储元件（1,2和3）。 为了加速在导体上的输出电压的建立，提供两个交叉连接的晶体管（22,23）以补充该导体的放电，该导体具有较低的电压，每个晶体管响应于一个上的电压 导体放电另一导体。 交叉连接晶体管的操作的正确时序由两个另外的晶体管（26,27）提供，其中它们的栅极分别连接到当存储元件已经实现了足够的电压充电时被布置成导通的导体。 当另外的晶体管中的任一个导通与两个交叉连接的晶体管串联的晶体管（24）导通时，使它们能够工作。

公开(公告)号：US07191199B2

公开(公告)日：2007-03-13

申请号：US10640453

申请日：2003-08-13

Applicant: Richard D. Simpson ,  Graeme Swanson ,  Konstantinos Venos

Inventor： Richard D. Simpson ,  Graeme Swanson ,  Konstantinos Venos

IPC: G06F15/00

CPC classification number: G06F7/544 ,  G06F2207/5442

Abstract: Computing an absolute difference includes receiving a first value and a second value. Propagate terms are determined according to the first value and the second value at one or more adders (24). The second value is subtracted from the first value using the propagate terms to yield a subtraction difference. It is determined at one or more correctors (26) whether the subtraction difference is negative. If the subtraction difference is negative, the subtraction difference is modified according to the propagate terms to compute an absolute difference between the first value and the second value. Otherwise, the subtraction difference is reported as the absolute difference between the first value and the second value.

Abstract translation: 计算绝对差异包括接收第一值和第二值。 根据在一个或多个加法器（24）处的第一值和第二值确定传播项。 使用传播项从第一个值中减去第二个值，以产生减法差。 在一个或多个校正器（26）中确定减法差是否为负。 如果减法差为负，则根据传播项修改减法差，以计算第一值和第二值之间的绝对差。 否则，减法差被报告为第一值和第二值之间的绝对差。

公开(公告)号：US06986089B2

公开(公告)日：2006-01-10

申请号：US10256723

申请日：2002-09-27

Applicant: Anthony M. Hill ,  Richard D. Simpson

Inventor： Anthony M. Hill ,  Richard D. Simpson

IPC: G01R31/28 ,  G06F13/38

CPC classification number: G01R31/318575 ,  G01R31/31721

Abstract: In a scannable D master-slave flip-flop circuit with synchronous preset or clear capability, the output of the slave latch is gated with the scan-enable signal to form the scan-data-output signal. This output gating of the scan-output data that allows for considerable simplification of the input logic. This simplification also provides for the reduction in both the size and the number of transistors in the input logic. This in turn is multiplied many tens of thousands of times in a complex processor chip, resulting in a substantial reduction in chip power and silicon area usage.

Abstract translation: 在具有同步预置或清除能力的可扫描D主从触发器电路中，从锁存器的输出通过扫描使能信号选通，形成扫描数据输出信号。 该输出门控的扫描输出数据允许相当简化的输入逻辑。 这种简化还提供了输入逻辑中的晶体管的尺寸和数量的减少。 这在复杂的处理器芯片中又相当于数万次，导致芯片功率和硅面积使用量大幅降低。

公开(公告)号：US5079742A

公开(公告)日：1992-01-07

申请号：US386849

申请日：1989-07-28

Applicant: Richard D. Simpson

Inventor： Richard D. Simpson

IPC: G11C17/12

CPC classification number: G11C17/12

Abstract: A read-only memory suitable for use as the control ROM of a microprocessor has each output line divided into first and second parts. Memory elements connected to the first parts are responsive to early-occurring input signals and memory elements connected to the second parts are responsive to late-occurring input signals. Switch means are provided to enable the output signals from the second parts of the output lines to be generated in response to a late-occurring input signal independently of the loading of the memory elements connected to the first parts of the output lines.

Abstract translation: 适合用作微处理器的控制ROM的只读存储器将每条输出线分成第一和第二部分。 连接到第一部分的存储元件响应于早期输入信号，并且连接到第二部分的存储元件响应于晚期输入信号。 提供开关装置，以使得来自输出线的第二部分的输出信号能够响应于晚期发生的输入信号而产生，而与连接到输出线的第一部分的存储元件的负载无关。

公开(公告)号：US5005193A

公开(公告)日：1991-04-02

申请号：US374194

申请日：1989-06-29

Applicant: Richard D. Simpson

Inventor： Richard D. Simpson

IPC: H03K5/15

CPC classification number: H03K5/15093

Abstract: A clock generating circuit for use in a signal processing circuit to enable it to be synchronized with other circuits in response to a reset signal uses a multi-state circuit which is cyclically stepped through its states by a clock drive signal and a decoder responsive to the state of the multi-state circuit to produce the required clock pulses. The reset signal is used to stop the multi-state circuit at a particular state and hold it there for a period of time enabling other similar clock pulse generating circuits to reach the same state and be held there. At the end of the period of time the multi-state circuits resume their cyclic stepping with all the circuits in synchronism.

Abstract translation: 用于在信号处理电路中使其能够响应于复位信号与其它电路同步的时钟发生电路使用多状态电路，该多状态电路通过时钟驱动信号和解码器对其状态进行循环地步进， 状态电路以产生所需的时钟脉冲。 复位信号用于在特定状态下停止多状态电路并将其保持在一段时间，使得其他类似的时钟脉冲发生电路能够达到相同的状态并保持在那里。 在这段时间结束时，多状态电路与所有电路同步地恢复循环步进。

公开(公告)号：US4858167A

公开(公告)日：1989-08-15

申请号：US285359

申请日：1988-12-14

Applicant: Richard D. Simpson ,  Derek Roskell

Inventor： Richard D. Simpson ,  Derek Roskell

IPC: G06F7/50 ,  G06F7/506 ,  G06F7/508

CPC classification number: G06F7/506

Abstract: A binary adder circuit is described using dynamic transistor logic in which for high speed carry propagation the adder stages are grouped in pairs or larger numbers and additional dynamic logic means is provided in each group to control a single transistor connected in series in the carry propagation path over the group. The transistors used in the specific embodiments are MOS transistors, but some or all of these could be replaced by junction FET's or bipolar transistors.

Abstract translation: 使用动态晶体管逻辑来描述二进制加法器电路，其中对于高速进位传播，加法器级被成对或成对地分组，并且在每个组中提供附加的动态逻辑装置以控制在进位传播路径中串联连接的单个晶体管 在集团上。 在具体实施例中使用的晶体管是MOS晶体管，但是其中的一些或全部可以被结FET或双极晶体管代替。

公开(公告)号：US4849920A

公开(公告)日：1989-07-18

申请号：US839004

申请日：1986-03-12

Applicant: Richard D. Simpson ,  Michael D. Asal

Inventor： Richard D. Simpson ,  Michael D. Asal

IPC: G06F7/00 ,  G06F7/74 ,  G06F7/76 ,  H03M7/00

CPC classification number: G06F7/74

Abstract: The position of an end "1" bit in an input number is detected by applying the inverted bits in parallel to inputs of respective NOR gates (61 to 68), the other inputs of which are connected to the nodes of a chain of dynamic field effect transistors (A1 to A8) along which a "O" is propagated. The coincidence of two O's at the inputs of a NOR gate causes it to produce a "1" output representing the location of the end "1" of the input number. The outputs of the NOR gates (L1 to L8) are connected to the column conductors of an field effect transistor array (LA) which produces on the row conductors array in parallel, inverted, binary coded form a number corresponding to the position of the NOR gate producing a "1" output. The apparatus may be divided into several units (U1 to U4) responsive to adjacent groups of the bits of the input number each producing a representation of the location of the end "1" in its group. The units are coupled together so that a representation from a preceding unit blocks the output of a representation from a subsequent unit.

Abstract translation: 通过将反相位并行地并入到各个或非门（61至68）的输入端来检测输入号码中的“1”位的位置，其另一个输入端连接到动态域链的节点 效应晶体管（A1至A8），沿着该晶体管传播“O”。 两个O在NOR门的输入端的重合使得它产生一个“1”输出，表示输入号码的结尾“1”的位置。 NOR门（L1〜L8）的输出端连接到场效应晶体管阵列（LA）的列导体，该场效应晶体管阵列（LA）在行导体阵列上平行生成，反相，二进制编码形成对应于NOR 门产生“1”输出。 该装置可以响应于输入号码的相邻组的每一组而分成若干单元（U1至U4），每个单元产生其组中的端“1”的位置的表示。 这些单元耦合在一起，使得来自前一单元的表示阻止来自后续单元的表示的输出。

公开(公告)号：US4558232A

公开(公告)日：1985-12-10

申请号：US350958

申请日：1982-02-22

Applicant: Richard D. Simpson

Inventor： Richard D. Simpson

IPC: G01R31/317 ,  H03K5/153 ,  H03K5/24

CPC classification number: G01R31/31701

Abstract: An overvoltage detector circuit for connection to an input terminal of a microcomputer device or the like employs a bistable latch with two inputs, one connected to a reference potential and the other to the input terminal. When the inputs are gated, the latch flips to one state if the terminal is at an overvoltage, or the other state if the terminal is at zero or logic-1. This circuit may be used to institute a test mode for the microcomputer.

Abstract translation: 用于连接到微计算机装置等的输入端子的过电压检测器电路采用具有两个输入的双稳态锁存器，一个连接到参考电位，另一个连接到输入端子。 当输入选通时，如果端子处于过压状态，则锁存器翻转到一个状态，或者如果端子为零或逻辑1，则其它状态。 该电路可用于为微型计算机建立测试模式。

公开(公告)号：US20080219390A1

公开(公告)日：2008-09-11

申请号：US12028515

申请日：2008-02-08

Applicant: Richard D. Simpson ,  Michael S. Harwood ,  Patrick W. Bosshart

Inventor： Richard D. Simpson ,  Michael S. Harwood ,  Patrick W. Bosshart

IPC: H04L7/00

CPC classification number: H04L7/0062 ,  H04L7/033

Abstract: A thermometer code to sign and magnitude converter that is particularly useful in a flash ADC is provided. This comprises two conversion units. The first is a thermometer code to Gray code converter and the second a Gray code to sign and magnitude converter. Preferably, the Gray code is of a kind that has a sign bit and has the other bits symmetrically disposed about zero. This form is easily converted to a sign and magnitude code, which is advantageous as it reduces the latency of the converter, which is particularly useful at high data rates.

Abstract translation: 提供了在闪存ADC中特别有用的符号和幅度转换器的温度计代码。 这包括两个转换单元。 第一个是格雷码转换器的温度计代码，第二个是格雷码到符号和幅度转换器。 优选地，格雷码是具有符号位的类型，并且其他位对称地设置在零附近。 这种形式很容易转换为符号和幅度码，这是有利的，因为它减少了转换器的延迟，这在高数据速率下特别有用。

公开(公告)号：US20080205563A1

公开(公告)日：2008-08-28

申请号：US12028490

申请日：2008-02-08

Applicant: Richard D. Simpson ,  Nimal C. Warke

Inventor： Richard D. Simpson ,  Nimal C. Warke

IPC: H04B1/10

CPC classification number: H03H17/0261 ,  H04L25/03057 ,  H04L2025/03636

Abstract: The invention provides a particular construction for digital filters in which, instead of multiplying various ones of the digital samples by weights and adding the results together, one or more of the digital samples is inspected by a ranging unit, which then instructs an incrementing unit to increment, decrement or leave alone one of the samples to provide the result. In order to achieve very high data rates, the incremented and decremented values can be pre-prepared whilst the ranging unit makes its decision, and then a multiplexer responsive to the output of the ranging unit is used to select the appropriate one of the pre-prepared values.

Abstract translation: 本发明提供了一种用于数字滤波器的特定结构，其中，代替通过权重将各种数字样本相乘并将结果相加在一起，一个或多个数字样本由测距单元检查，测距单元然后指示增量单元 增加，减量或单独留下一个样品来提供结果。 为了实现非常高的数据速率，可以在测距单元进行判定的同时预先准备递增和递减的值，然后使用响应于测距单元的输出的多路复用器来选择预定义的适当的一个， 准备的价值观。