公开(公告)号：US20030056164A1

公开(公告)日：2003-03-20

申请号：US09954637

申请日：2001-09-14

Applicant: STMicroelectronics Limited

Inventor： Christophe Lauga

IPC: G01R031/28

CPC classification number: G01R31/318536 ,  G01R31/318547 ,  G01R31/318572

Abstract: A semiconductor integrated circuit, including a test scan arrangement has a plurality of scan chains arranged in pairs. These scan chains have input terminals for receiving test patterns, and outputs provided to compression logic such as a distributed XOR tree multiple input shift register to provide an output which is a compressed signal derived from the output test patterns. In an alternative configuration, the first scan chain of each pair is connected to the second scan chain of each pair, and the input terminal of the second scan chain becomes the output terminal. Thereby creating a longer scan chain of the first and second scan chains together with one input terminal and one output terminal. The two loads allow for efficient scanning in the first mode, or debugging to determine the position of a fault in the second mode.

Abstract translation: 包括测试扫描装置的半导体集成电路具有成对布置的多个扫描链。 这些扫描链具有用于接收测试图案的输入端子，以及提供给诸如分布式异或树多输入移位寄存器之类的压缩逻辑的输出，以提供作为从输出测试图案导出的压缩信号的输出。 在替代配置中，每对的第一扫描链连接到每对的第二扫描链，并且第二扫描链的输入端变为输出端。 从而创建第一和第二扫描链的更长的扫描链以及一个输入端和一个输出端。 两个负载允许在第一模式下进行有效的扫描，或者调试以确定第二模式中故障的位置。

公开(公告)号：US20020196710A1

公开(公告)日：2002-12-26

申请号：US10157731

申请日：2002-05-29

Applicant: STMicroelectronics Limited

Inventor： Andrew Dellow ,  Paul Elliott

IPC: G06F001/04 ,  G04F005/00

CPC classification number: G06F1/08

Abstract: A clock source selector for selecting either a first clock signal A or a second clock signal B in accordance with a switch request signal includes three retiming circuits each consisting of two clocked flip-flops. The switch request signal is first retimed relative to clock A to give a signal P, is then retimed relative to clock B to give a signal Q, and finally is retimed relative to clock A to give a signal R. Selector circuitry operates such that when signal Q is asserted, the second clock signal B is output, when neither signal P nor signal R, as combined by a NOR gate, are asserted, the first clock signal A is output, and at other times a zero level is output. The clock source selector can be used in an integrated circuit to form a glitch-free multiplexer.

Abstract translation: 用于根据切换请求信号选择第一时钟信号A或第二时钟信号B的时钟源选择器包括三个重新定时电路，每个由两个时钟触发器组成。 开关请求信号相对于时钟A首先被重新定时以给出信号P，相对于时钟B被重新定时以给出信号Q，并且最后相对于时钟A被重新定时以给出信号R.选择器电路操作使得当 信号Q被置位，当第二时钟信号B被输出时，当由或非门组合的信号P和信号R都不被断言时，输出第一时钟信号A，并且在其它时间输出零电平。 时钟源选择器可用于集成电路中以形成无毛刺多路复用器。

公开(公告)号：US20020191725A1

公开(公告)日：2002-12-19

申请号：US10106899

申请日：2002-03-25

Applicant: STMicroelectronics Limited

Inventor： Andrew Dellow

IPC: H03D003/24

CPC classification number: H03D13/004

Abstract: A digital phase comparator circuit that determines and adjusts the relative phase of two digital clock signals derived from the same digital clock. The circuit having two inputs, one connected to receive each of the clock signals to be compared and including a latch circuit to receive one clock signal at the clock input, and the other clock signal at a data input. The latch circuit is arranged so that the output is equal to the signal at the data input when measured at the clock edge. The output is therefore a logic null1null when the second clock leads the first clock, and a logic null0null when the second clock lags the first clock.

Abstract translation: 数字相位比较器电路，用于确定并调整从相同数字时钟导出的两个数字时钟信号的相对相位。 该电路具有两个输入端，一个连接到接收要比较的每个时钟信号，并且包括用于在时钟输入端接收一个时钟信号的锁存电路，以及数据输入端的另一个时钟信号。 锁存电路被布置为使得当在时钟边沿测量时，输出等于数据输入端的信号。 因此，当第二个时钟引导第一个时钟时，输出为逻辑“1”，当第二个时钟延迟第一个时钟时，输出为逻辑“0”。

公开(公告)号：US20020005733A1

公开(公告)日：2002-01-17

申请号：US09949703

申请日：2001-09-10

Applicant: STMicroelectronics Limited

Inventor： William B. Barnes

IPC: H03K017/16

CPC classification number: H01L29/0634 ,  H03K3/356113 ,  H03K17/102

Abstract: A switching circuit is discussed that has an improved switching time in comparison with switching circuits of a known type. The circuit comprises three switches connected in series, the first switch being connected to an upper power supply and the third switch being connected to a lower power supply. The output of the circuit is connected to a circuit node located at the connection between the second and third switch. The input to the switching circuit is also connected to the third switch and additionally connected to a control circuit which provides a further output to control the first switch. The second switch is responsive to the voltage at the circuit node such that the second switch only conducts when the voltage at the output node falls below the upper supply voltage. This has the effect that the first switch is effectively isolated from the third switch during switching and allows a time delay during which the first switch is switched off under control of the control circuit and the second switch switches on. The provision of the voltage dependent second switch eliminates any nullcurrent battlesnull occurring between the first and third switch during switching.

Abstract translation: 讨论了与已知类型的开关电路相比具有改进的开关时间的开关电路。 电路包括串联连接的三个开关，第一开关连接到上电源，第三开关连接到较低电源。 电路的输出连接到位于第二和第三开关之间的连接处的电路节点。 开关电路的输入也连接到第三开关，并且还连接到控制电路，该控制电路提供另外的输出以控制第一开关。 第二开关响应于电路节点处的电压，使得第二开关仅在输出节点处的电压下降到低于上电源电压时才导通。 这具有在开关期间第一开关与第三开关有效隔离的作用，并且允许第一开关在控制电路的控制下被切断并且第二开关导通的时间延迟。 提供依赖于电压的第二开关消除了在切换期间在第一和第三开关之间发生的任何“当前的战斗”。

公开(公告)号：US20040156507A1

公开(公告)日：2004-08-12

申请号：US10705782

申请日：2003-11-10

Applicant: STMicroelectronics Limited

Inventor： Andrew Dellow ,  Rodrigo Cordero

IPC: H04L009/00

CPC classification number: H04N21/42623 ,  H04N21/26613 ,  H04N21/4623

Abstract: A semiconductor integrated circuit for the processing of conditional access television signals, the circuit including an input interface for receiving encrypted television signals and an output interface for output of decrypted television signals. Control signals broadcast with the television signals include control words and common keys. The common keys are received in encrypted form, encrypted according to a secret key unique to each semiconductor integrated circuit. The input interface is connected to a decryption circuit whereby the only manner of providing the common keys to the circuit are in encrypted form encrypted according to the secret key. Due to the monolithic nature of the circuit, no secrets are exposed and the system is secure.

Abstract translation: 一种用于处理条件接收电视信号的半导体集成电路，该电路包括用于接收加密的电视信号的输入接口和用于输出解密的电视信号的输出接口。 用电视信号广播的控制信号包括控制字和公共密钥。 公共密钥以加密形式接收，根据每个半导体集成电路独有的秘密密钥进行加密。 输入接口连接到解密电路，由此向电路提供公共密钥的唯一方式是根据密钥加密的加密形式。 由于电路的整体性质，没有暴露的秘密和系统是安全的。

公开(公告)号：US20040148583A1

公开(公告)日：2004-07-29

申请号：US10352799

申请日：2003-01-27

Applicant: STMicroelectronics Limited

Inventor： Andrew Hulbert ,  Enrico Gregoratto

IPC: G06F017/50

CPC classification number: G06F17/5068 ,  G06F17/505

Abstract: A method of arranging an integrated circuit to correct for hold time errors comprises fixing the position of existing cells in a design, determining hold time errors required to be corrected and placing buffer cells in spaces in the existing design. By placing buffer cells in spaces in the existing design, rather than moving cells in the existing design, the hold time can be corrected without changing the critical path.

Abstract translation: 布置集成电路以校正保持时间误差的方法包括：将设计中的现有单元的位置固定，确定需要校正的保持时间误差，并将缓冲单元放置在现有设计中的空格中。 通过将现有设计中的缓冲区放置在空格中，而不是在现有设计中移动单元格，可以在不改变关键路径的情况下更正保持时间。

公开(公告)号：US20040120385A1

公开(公告)日：2004-06-24

申请号：US10632566

申请日：2003-08-01

Applicant: STMicroelectronics Limited ,  STMicroelectronics S.r.I.

Inventor： Philip Mattos ,  Marco Losi

IPC: H04B001/707

CPC classification number: H04B1/7085 ,  G01S19/29 ,  G01S19/30 ,  H03H17/0664 ,  H04B1/70753 ,  H04B1/709 ,  H04B2201/70715

Abstract: A semiconductor integrated circuit for processing a plurality of received broadcast signals, such as GPS signals, is operable in two modes: acquisition and tracking. In an acquisition mode, sample reducer combines samples of a received signal for correlation with a locally generated version of a GPS code. In a tracking mode, the sampled signal is provided direct to the correlators without sample reduction. The same correlators are thereby used to increase acquisition speed.

Abstract translation: 用于处理诸如GPS信号的多个接收的广播信号的半导体集成电路可以以两种模式进行操作：采集和跟踪。 在采集模式中，采样减速器组合接收信号的样本，以便与本地生成的GPS码版本进行相关。 在跟踪模式中，采样信号直接提供给相关器而不需要样本减少。 因此，使用相同的相关器来提高采集速度。

公开(公告)号：US20030158882A1

公开(公告)日：2003-08-21

申请号：US10322197

申请日：2002-12-17

Applicant: STMicroelectronics Limited

Inventor： Simon Knowles

IPC: G06F007/50

CPC classification number: G06F7/508 ,  G06F2207/5063

Abstract: A method of designing an addition circuit, and an addition circuit designed according to the method are described. The design technique is optimised to facilitate design of an addition circuit of minimum depth. The design technique takes into account the number of logical stages of the addition circuit and the manner in which those stages are connected by spanning paths to create fan-out nodes. The number of fan-out nodes per level can be optimized. For bit lengths n, the number (mnull2) of logical stages is nnull2mnull1 and for bit lengths n not of a binary order, the number (mnull2) of logical stages is nbonull2mnull1, where nbo is the next largest binary order after n.

Abstract translation: 描述了根据该方法设计的加法电路的设计方法和加法电路。 优化设计技术，以便于设计最小深度的加法电路。 设计技术考虑了加法电路的逻辑级数和通过跨越路径连接这些级的方式来创建扇出节点。 可以优化每个级别的扇出节点数量。 对于位长度n，逻辑级数（m + 2）为n = 2m + 1，对于不是二进制顺序的位长度n，逻辑级的数量（m + 2）为nbo = 2m + 1，其中 nbo是n之后的下一个最大的二进制顺序。

公开(公告)号：US20030140338A1

公开(公告)日：2003-07-24

申请号：US10206381

申请日：2002-07-26

Applicant: STMicroelectronics Limited

Inventor： Antony Bowers ,  Richard Shann

IPC: G06F009/44

CPC classification number: G06F8/54

Abstract: Call frame information is used by debugging software. It records how to restore the parent stack frame at any point during execution of a program. It is normally generated during compilation and stored in the executable in a compressed format, consisting of sequences of instructions that describe how the current call frame changes during execution of each function. Described herein is a means of generating call frame information at link time, using linker macro calls generated by a small set of assembler macros.

Abstract translation: 呼叫帧信息由调试软件使用。 它记录了在执行程序期间的任何时候如何恢复父堆栈帧。 它通常在编译期间生成并以压缩格式存储在可执行文件中，该格式由描述当前调用帧在每个功能执行期间如何改变的指令序列组成。 这里描述的是使用由一组汇编器宏生成的链接器宏调用在链接时产生呼叫帧信息的手段。

公开(公告)号：US20030068000A1

公开(公告)日：2003-04-10

申请号：US10247263

申请日：2002-09-18

Applicant: STMicroelectronics Limited

Inventor： Robert Geoffrey Warren

IPC: G06F003/00 ,  H04L007/00

CPC classification number: G01R31/318552 ,  G01R31/31937

Abstract: A system comprising a host, a target and connection means therebetween. The host has means for providing a clock signal, first output means for outputting said clock signal to said target via said connection means and second output means for outputting data to said target via said connection means, said data being clocked out by said clock signal, said target having first input means for receiving said clock signal from said host, second input means for receiving said data from said host and first output means for outputting data to said host via said connection means. The host further comprises input means for receiving said data from said target, and oversampling means for oversampling the received data from the target and controlling the clocking in of said data received from said target in dependence on said oversampling.

Abstract translation: 一种包括主机，目标和它们之间的连接装置的系统。 主机具有用于提供时钟信号的装置，用于经由所述连接装置将所述时钟信号输出到所述目标的第一输出装置和用于经由所述连接装置将数据输出到所述目标的第二输出装置，所述数据由所述时钟信号输出， 所述目标具有用于从所述主机接收所述时钟信号的第一输入装置，用于从所述主机接收所述数据的第二输入装置和用于经由所述连接装置向所述主机输出数据的第一输出装置。 主机还包括用于从所述目标接收所述数据的输入装置，以及过采样装置，用于对来自目标的接收数据进行过采样，并根据所述过采样来控制从所述目标接收的所述数据的时钟。