公开(公告)号：US07302658B2

公开(公告)日：2007-11-27

申请号：US10765276

申请日：2004-01-28

申请人： Sadami Takeoka ,  Mitsuyasu Ohta

发明人： Sadami Takeoka ,  Mitsuyasu Ohta

IPC分类号： G06F17/50

CPC分类号： G11B20/18 ,  G01R31/318328

摘要： In evaluating of the quality of test sequences for delay faults, when all the delay faults are equally regarded, the process of detecting the delay faults deserving to be detected and those not so deserving to be detected cannot be reflected on the quality evaluation for the test sequences. To solve the problem, a “design delay value” on a signal path, on which a corresponding delay fault is defined, is weighted. This invention thus provides “methods of evaluating the quality of test sequences for delay faults” capable of evaluating the quality of the “delay fault test sequences” with more accuracy.

摘要翻译： 在对延迟故障的测试序列的质量进行评估时，当所有的延迟故障都被同等地考虑时，检测到的延迟故障检测过程和不值得检测的延迟故障的过程不能反映在测试的质量评估中 序列。 为了解决这个问题，在相应的延迟故障被定义的信号路径上的“设计延迟值”被加权。 因此，本发明提供了能够更精确地评​​估“延迟故障测试序列”的质量的“评估延迟故障的测试序列的质量的方法”。

公开(公告)号：US07032196B2

公开(公告)日：2006-04-18

申请号：US10828230

申请日：2004-04-21

申请人： Sadami Takeoka ,  Mitsuyasu Ohta ,  Osamu Ichikawa ,  Masayoshi Yoshimura

发明人： Sadami Takeoka ,  Mitsuyasu Ohta ,  Osamu Ichikawa ,  Masayoshi Yoshimura

IPC分类号： G06F17/50 ,  H01L23/58 ,  G01R31/28

CPC分类号： G01R31/28 ,  G01R31/318505 ,  G01R31/318538 ,  G01R31/318558 ,  G06F17/50 ,  G11C5/02 ,  G11C5/025 ,  G11C29/48 ,  G11C2029/3202 ,  H01L23/12

摘要： A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.

公开(公告)号：US20050028051A1

公开(公告)日：2005-02-03

申请号：US10766951

申请日：2004-01-30

申请人： Sadami Takeoka ,  Seiji Kajihara

发明人： Sadami Takeoka ,  Seiji Kajihara

IPC分类号： G01R31/28 ,  G01R31/30 ,  G01R31/3181 ,  G06F17/50 ,  G06K5/04 ,  G11B5/00 ,  G11B20/20

CPC分类号： G01R31/3016

摘要： All untestable delay faults are hardly calculated. Thus, when the fault coverage of an test sequence for a delay fault is calculated, the fault coverage is not calculated without excluding the number of untestable faults. Accordingly the fault coverage does not correctly represent a test quality. The delay faults are partly selected to analyze how many untestable delay faults exist among the selected delay faults. Thus, the, number of untestable delay faults included all the delay faults are estimated. Thus, a method for evaluating a delay fault test quality for calculating the fault coverage that correctly represents the test quality by using this value is provided.

摘要翻译： 所有不可逾越的延迟故障几乎不计算。 因此，当计算延迟故障的测试序列的故障覆盖时，不计算故障覆盖范围，而不排除不可测故障的数量。 因此，故障覆盖不能正确表示测试质量。 部分选择延迟故障来分析所选延迟故障中存在多少不可测延迟故障。 因此，估计了不可逾越的延迟故障的数量，包括所有的延迟故障。 因此，提供了一种通过使用该值来评估用于计算正确表示测试质量的故障覆盖的延迟故障测试质量的方法。

公开(公告)号：US06734549B2

公开(公告)日：2004-05-11

申请号：US10187269

申请日：2002-07-02

申请人： Sadami Takeoka ,  Mitsuyasu Ohta ,  Osamu Ichikawa ,  Masayoshi Yoshimura

发明人： Sadami Takeoka ,  Mitsuyasu Ohta ,  Osamu Ichikawa ,  Masayoshi Yoshimura

IPC分类号： H01L2312

CPC分类号： G01R31/28 ,  G01R31/318505 ,  G01R31/318538 ,  G01R31/318558 ,  G06F17/50 ,  G11C5/02 ,  G11C5/025 ,  G11C29/48 ,  G11C2029/3202 ,  H01L23/12

摘要： A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.

摘要翻译： 通过将多个芯片智能特性（IP）安装在公共半导体布线基板上构成的半导体器件，测试器件的方法和安装芯片IP的方法。 提供了可以安装芯片IP的硅布线基板。 通过连接触发器在硅布线基板上形成用于边界扫描测试的电路。 触发器连接到布线并被布置成测试布线中的连接。 整个IP On Super Sub（IPOS）设备或每个芯片IP可以被布置成便于在芯片IP的内部电路上进行扫描测试，内置自检（BIST）等。

公开(公告)号：US06615389B1

公开(公告)日：2003-09-02

申请号：US09561342

申请日：2000-04-28

申请人： Mitsuyasu Ohta ,  Sadami Takeoka ,  Osamu Ichikawa

发明人： Mitsuyasu Ohta ,  Sadami Takeoka ,  Osamu Ichikawa

IPC分类号： G06F1750

CPC分类号： G06F17/5045

摘要： In response to a design request, fault detection strategy optimizing means selects RT-VCs and a fault detection method from a VCDB. The design request includes: requirements for a system LSI (e.g., area, number of pins, test time and information about the weights of prioritized constraints); and VC information. The fault detection strategy optimizing means performs computations for optimization in view of various parameters, thereby specifying a best fault detection strategy and a method of constructing a single-chip fault detection controller. On the VCDB, multiple VCs associated with the same function and mutually different test techniques are stored. By weighting the parameters affecting a test cost in accordance with a user defined priority order, a test technique of the type minimizing the total test cost can be selected from the VCDB.

摘要翻译： 响应于设计请求，故障检测策略优化装置从VCDB中选择RT-VC和故障检测方法。 设计请求包括：对系统LSI的要求（例如，区域，引脚数，测试时间和关于优先约束的权重的信息）; 和VC信息。 故障检测策略优化装置根据各种参数进行优化计算，从而指定最佳故障检测策略和构建单片故障检测控制器的方法。 在VCDB上，存储与相同功能和相互不同的测试技术相关联的多个VC。 通过根据用户定义的优先顺序加权影响测试成本的参数，可以从VCDB中选择最小化总测试成本的类型的测试技术。

公开(公告)号：US5430736A

公开(公告)日：1995-07-04

申请号：US868737

申请日：1992-04-15

申请人： Sadami Takeoka ,  Akira Motohara

发明人： Sadami Takeoka ,  Akira Motohara

IPC分类号： G01R31/3183 ,  G01R31/28 ,  G01R31/3185 ,  G06F11/22 ,  G06F11/263

CPC分类号： G01R31/318586 ,  G01R31/318547 ,  G01R31/318392

摘要： In an apparatus for generating a test pattern for a sequential logic circuit including a plurality of storage elements each storage element storing a logical value of one bit wherein logical values of bits of the plurality of storage elements being represented by a state, first external input values are generated so that a transition process is performed from a second state of the plurality of storage elements to a first state thereof, and second external input values are generated so hat a transition process is performed from a third state of the plurality of storage elements to the first state thereof. Thereafter, third external input values are generated so that a transition process is performed from a fourth state of the plurality of storage elements to the first state thereof. After setting the fourth state as the first state, name data of storage elements corresponding to bits of different states between the second and third states are stored in a storage unit. After setting the third state as the first state, there is increased a degree of requesting a scan operation for each of the storage elements, name data of which have been stored in the storage unit. Then, storage elements to be scanned are selected for generating an improved test pattern based on the degree of requesting the scan operation.

摘要翻译： 在用于生成包括多个存储元件的顺序逻辑电路的测试图案的装置中，每个存储元件存储一位的逻辑值，其中多个存储元件的位的逻辑值由状态表示，第一外部输入值 被产生，使得从多个存储元件的第二状态到其第一状态执行转换处理，并且产生第二外部输入值，从而从多个存储元件的第三状态执行转换处理， 其第一个状态。 此后，产生第三外部输入值，使得从多个存储元件的第四状态到其第一状态执行转换处理。 在将第四状态设置为第一状态之后，将与第二状态和第三状态之间的不同状态的位对应的存储元件的名称数据存储在存储单元中。 在将第三状态设置为第一状态之后，对存储单元中已存储的每个存储元件的每个存储元件请求扫描操作的程度增加。 然后，选择要扫描的存储元件，以便基于请求扫描操作的程度产生改进的测试图案。

公开(公告)号：US07613972B2

公开(公告)日：2009-11-03

申请号：US11585778

申请日：2006-10-25

申请人： Sadami Takeoka ,  Shinichi Yoshimura

发明人： Sadami Takeoka ,  Shinichi Yoshimura

IPC分类号： G01R31/28

CPC分类号： G01R31/318552

摘要： A semiconductor integrated circuit comprises a combinational circuit section having a combinational circuit, a scan path circuit for inputting and outputting a value from and to the combinational circuit section in accordance with a scan enable signal and in synchronization with a clock signal, and a clock control section for generating and outputting a predetermined number of pulses as the clock signal after a predetermined period has passed since a time when an output command signal was received. The clock control section has an oscillator circuit for generating and outputting the pulse, and is configured to output a last pulse of the predetermined number of pulses in a manner which holds a logical value immediately after an active edge for the scan path circuit.

摘要翻译： 半导体集成电路包括具有组合电路的组合电路部分，用于根据扫描使能信号并与时钟信号同步地输入和输出组合电路部分的值的扫描路径电路，以及时钟控制 从接收到输出命令信号的时刻起经过预定​​时间段之后，生成并输出预定数量的脉冲作为时钟信号。 时钟控制部分具有用于产生和输出脉冲的振荡器电路，并且被配置为以保持紧接在扫描路径电路的有效边沿之后的逻辑值的方式输出预定数量的脉冲的最后脉冲。

公开(公告)号：US07590908B2

公开(公告)日：2009-09-15

申请号：US12390761

申请日：2009-02-23

申请人： Takashi Ishimura ,  Sadami Takeoka

发明人： Takashi Ishimura ,  Sadami Takeoka

IPC分类号： G01R31/28 ,  G06F11/00 ,  G06F1/26 ,  G01F1/00

CPC分类号： G01R31/318575

摘要： In a semiconductor integrated circuit, power source wiring for supplying power supply voltage to a plurality of flip flop circuits, and power source wiring for supplying different power supply voltage to a combinational circuit are provided individually, so that the power supply to the flip flop circuits and the power supply to the combinational circuit can be performed separately from, and independently of, each other. During shift operation in scan testing, the power supply voltage to the combinational circuit is set to a low voltage or cut off, thereby suppressing the amount of power consumed by the combinational circuit portion during the shift operation. At the same time, the power supply voltage to the flip flop circuits is set to a high voltage during the shift operation.

公开(公告)号：US20070113131A1

公开(公告)日：2007-05-17

申请号：US11585778

申请日：2006-10-25

申请人： Sadami Takeoka ,  Shinichi Yoshimura

发明人： Sadami Takeoka ,  Shinichi Yoshimura

IPC分类号： G01R31/28

CPC分类号： G01R31/318552

摘要： A semiconductor integrated circuit comprises a combinational circuit section having a combinational circuit, a scan path circuit for inputting and outputting a value from and to the combinational circuit section in accordance with a scan enable signal and in synchronization with a clock signal, and a clock control section for generating and outputting a predetermined number of pulses as the clock signal after a predetermined period has passed since a time when an output command signal was received. The clock control section has an oscillator circuit for generating and outputting the pulse, and is configured to output a last pulse of the predetermined number of pulses in a manner which holds a logical value immediately after an active edge for the scan path circuit.

摘要翻译： 半导体集成电路包括具有组合电路的组合电路部分，用于根据扫描使能信号并与时钟信号同步地输入和输出组合电路部分的值的扫描路径电路，以及时钟控制 从接收到输出命令信号的时刻起经过预定​​时间段之后，生成并输出预定数量的脉冲作为时钟信号。 时钟控制部分具有用于产生和输出脉冲的振荡器电路，并且被配置为以保持紧接在扫描路径电路的有效边沿之后的逻辑值的方式输出预定数量的脉冲的最后脉冲。

公开(公告)号：US07171600B2

公开(公告)日：2007-01-30

申请号：US10828263

申请日：2004-04-21

申请人： Sadami Takeoka ,  Mitsuyasu Ohta ,  Osamu Ichikawa ,  Masayoshi Yoshimura

发明人： Sadami Takeoka ,  Mitsuyasu Ohta ,  Osamu Ichikawa ,  Masayoshi Yoshimura

IPC分类号： G01R31/28

CPC分类号： G01R31/28 ,  G01R31/318505 ,  G01R31/318538 ,  G01R31/318558 ,  G06F17/50 ,  G11C5/02 ,  G11C5/025 ,  G11C29/48 ,  G11C2029/3202 ,  H01L23/12

摘要： An apparatus for testing a semiconductor device by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, including a silicon wiring substrate on which the chip IPs are mounted. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip-flops to wiring, which are arranged to test connections in the wiring. An IP on Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.

摘要翻译： 一种用于通过在公共半导体布线基板上安装多个芯片智能特性（IP）来测试半导体器件的装置，包括安装有芯片IP的硅布线基板。 通过将触发器连接到布线来测试布线中的连接，在硅布线基板上形成用于边界扫描测试的电路。 可以安排IP超级（IPOS）设备上的IP或每个芯片IP，以便在芯片IP的内部电路上进行扫描测试，内置自检（BIST）等。