摘要:
A semiconductor integrated circuit of the present invention is provided with a clock control portion having a clock generation portion for generating a clock signal and an output command signal input portion for receiving a clock output command signal from the outside, and an internal circuit controlled by an output clock signal that is output from the clock control portion, and the clock control portion is configured so that it outputs the output clock signal to the internal circuit when a certain time period has passed from a time when the output command signal is received.
摘要:
A semiconductor integrated circuit of the present invention is provided with a clock control portion having a clock generation portion for generating a clock signal and an output command signal input portion for receiving a clock output command signal from the outside, and an internal circuit controlled by an output clock signal that is output from the clock control portion, and the clock control portion is configured so that it outputs the output clock signal to the internal circuit when a certain time period has passed from a time when the output command signal is received.
摘要:
An apparatus for testing a semiconductor device by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, including a silicon wiring substrate on which the chip IPs are mounted. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip-flops to wiring, which are arranged to test connections in the wiring. An IP on Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.
摘要:
A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.
摘要翻译:通过将多个芯片智能特性(IP)安装在公共半导体布线基板上构成的半导体器件,测试器件的方法和安装芯片IP的方法。 提供了可以安装芯片IP的硅布线基板。 通过连接触发器在硅布线基板上形成用于边界扫描测试的电路。 触发器连接到布线并被布置成测试布线中的连接。 整个IP On Super Sub(IPOS)设备或每个芯片IP可以被布置成便于在芯片IP的内部电路上进行扫描测试,内置自检(BIST)等。
摘要:
A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.
摘要:
A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.
摘要翻译:通过将多个芯片智能特性(IP)安装在公共半导体布线基板上构成的半导体器件,测试器件的方法和安装芯片IP的方法。 提供了可以安装芯片IP的硅布线基板。 通过连接触发器在硅布线基板上形成用于边界扫描测试的电路。 触发器连接到布线并被布置成测试布线中的连接。 整个IP On Super Sub(IPOS)设备或每个芯片IP可以被布置成便于在芯片IP的内部电路上进行扫描测试,内置自检(BIST)等。
摘要:
A semiconductor integrated circuit contains a resistance element, wherein a low resistance region of a first conductivity type, employed for a circuit resistance, is formed within a high resistance region of a second conductivity type, opposite to the first conductivity type. The low resistance region and the high resistance region are connected in parallel, so as to prevent the formation of a parasitic transistor and a parasitic thyristor.
摘要:
In an input level converter for TTL--CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS--TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.
摘要:
In an input level converter for TTL-CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS-TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.
摘要:
In an input level converter for TTL - CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS - TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.