公开(公告)号：US20130067200A1

公开(公告)日：2013-03-14

申请号：US13619919

申请日：2012-09-14

申请人： Salvador PALANCA ,  Stephen A. FISCHER ,  Subramaniam MAIYURAN ,  Shekoufeh QAWAMI

发明人： Salvador PALANCA ,  Stephen A. FISCHER ,  Subramaniam MAIYURAN ,  Shekoufeh QAWAMI

IPC分类号： G06F9/312

CPC分类号： G06F9/3836 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/3012 ,  G06F9/30145 ,  G06F9/3808 ,  G06F9/3812 ,  G06F9/3834 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3867 ,  G06F2009/45583 ,  G06F2009/45591

摘要： A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.

公开(公告)号：US06842180B1

公开(公告)日：2005-01-11

申请号：US09665923

申请日：2000-09-20

申请人： Subramaniam Maiyuran ,  Vivek Garg ,  Jagannath Keshava ,  Salvador Palanca

发明人： Subramaniam Maiyuran ,  Vivek Garg ,  Jagannath Keshava ,  Salvador Palanca

IPC分类号： G06F12/08 ,  G06F15/167

CPC分类号： G09G5/001 ,  G06F12/0862 ,  G06F12/0897 ,  G06F2212/6022 ,  G06F2212/6026 ,  G09G5/363 ,  G09G5/39

摘要： An electronic device that has an integrated central processing unit (CPU) including a pre-fetch stride analyzer and an out-of-order engine is provided. The electronic device also has a graphics engine, having graphics memory, that is coupled to the integrated CPU. A main memory that is coupled to a memory controller is provided. The memory controller is also coupled to the CPU and the graphics engine. The device has a host address decoder coupled to the integrated CPU. A front side bus (FSB) is provided that is coupled to the integrated CPU and the host address decoder. Also provided is a plurality of memory components. Accordingly, either the plurality of memory components or the graphics memory can be shared to perform alternate memory functions. Additionally, a method is provided that determines allocation availability between memory components in an integrated computer processing unit. The method also shares an available memory component as a pre-fetch buffer and another available memory component as a victim cache.

摘要翻译： 提供具有集成中央处理单元（CPU）的电子设备，其包括预取步幅分析器和无序引擎。 电子设备还具有连接到集成CPU的具有图形存储器的图形引擎。 提供耦合到存储器控制器的主存储器。 存储器控制器还耦合到CPU和图形引擎。 该设备具有耦合到集成CPU的主机地址解码器。 提供了前置总线（FSB），其耦合到集成CPU和主机地址解码器。 还提供了多个存储器组件。 因此，可以共享多个存储器组件或图形存储器以执行备用存储器功能。 此外，提供了一种确定集成计算机处理单元中的存储器组件之间的分配可用性的方法。 该方法还将可用存储器组件作为预取缓冲区和另一可用存储器组件共享作为受害缓存。

公开(公告)号：US06772291B2

公开(公告)日：2004-08-03

申请号：US10206748

申请日：2002-07-26

申请人： Salvador Palanca ,  Subramaniam Maiyuran

发明人： Salvador Palanca ,  Subramaniam Maiyuran

IPC分类号： G06F1212

CPC分类号： G06F12/0848 ,  G06F12/123

摘要： A method and apparatus for cache replacement in a multiple variable-way associative cache is disclosed. The method according to the present techniques partitions a cache array dynamically based upon requests for memory from an integrated device having a plurality of processors.

摘要翻译： 公开了一种用于多可变方式关联高速缓存中的高速缓存替换的方法和装置。 根据本技术的方法基于来自具有多个处理器的集成设备对存储器的请求而动态地划分高速缓存阵列。

公开(公告)号：US06584547B2

公开(公告)日：2003-06-24

申请号：US09803357

申请日：2001-03-09

申请人： Salvador Palanca ,  Niranjan L. Cooray ,  Angad Narang ,  Vladimir Pentkovski ,  Steve Tsai

发明人： Salvador Palanca ,  Niranjan L. Cooray ,  Angad Narang ,  Vladimir Pentkovski ,  Steve Tsai

IPC分类号： G06F1200

CPC分类号： G06F12/0875 ,  G06F12/0862 ,  G06F12/0864 ,  G06F12/126

摘要： A method and system for providing cache memory management. The system comprises a main memory, a processor coupled to the main memory, and at least one cache memory coupled to the processor for caching of data. The at least one cache memory has at least two cache ways, each comprising a plurality of sets. Each of the plurality of sets has a bit which indicates whether one of the at least two cache ways contains non-temporal data. The processor accesses data from one of the main memory or the at least one cache memory.

公开(公告)号：US06546462B1

公开(公告)日：2003-04-08

申请号：US09475759

申请日：1999-12-30

申请人： Salvador Palanca ,  Stephen A. Fischer ,  Subramaniam Maiyuran

发明人： Salvador Palanca ,  Stephen A. Fischer ,  Subramaniam Maiyuran

IPC分类号： G06F1200

CPC分类号： G06F12/0811 ,  G06F12/0804

摘要： A system and method for flushing a cache line associated with a linear memory address from all caches in the coherency domain. A cache controller receives a memory address, and determines whether the memory address is stored within the closest cache memory in the coherency domain. If a cache line stores the memory address, it is flushed from the cache. The flush instruction is allocated to a write-combining buffer within the cache controller. The write-combining buffer transmits the information to the bus controller. The bus controller locates instances of the memory address stored within external and intel cache memories within the coherency domain; these instances are flushed. The flush instruction can then be evicted from the write-combining buffer. Control bits may be used to indicate whether a write-combining buffer is allocated to the flush instruction, whether the memory address is stored within the closest cache memory, and whether the flush instruction should be evicted from the write-combining buffer.

摘要翻译： 一种用于从一致性域中的所有高速缓存中刷新与线性存储器地址相关联的高速缓存行的系统和方法。 高速缓存控制器接收存储器地址，并且确定存储器地址是否存储在相干域中最接近的高速缓冲存储器中。 如果缓存行存储内存地址，则从缓存中刷新。 刷新指令被分配给高速缓存控制器内的写入组合缓冲器。 写合成缓冲器将信息发送到总线控制器。 总线控制器定位存储在相干域内的外部和英特尔高速缓存存储器中的存储器地址的实例; 这些实例被刷新。 然后可以从写入组合缓冲器中逐出驱动刷新指令。 控制位可以用于指示是否将写入组合缓冲器分配给闪存指令，存储器地址是否存储在最接近的高速缓冲存储器中，以及是否应该从写入组合缓冲器中驱逐刷新指令。

公开(公告)号：US06526499B2

公开(公告)日：2003-02-25

申请号：US09758486

申请日：2001-01-10

申请人： Salvador Palanca ,  Shekoufeh Qawami ,  Niranjan L. Cooray ,  Angad Narang ,  Subramaniam Maiyuran

发明人： Salvador Palanca ,  Shekoufeh Qawami ,  Niranjan L. Cooray ,  Angad Narang ,  Subramaniam Maiyuran

IPC分类号： G06F930

CPC分类号： G06F9/3857 ,  G06F9/30047 ,  G06F9/3824 ,  G06F9/3834 ,  G06F13/1668

摘要： The present invention discloses a method and apparatus for implementing a senior load instruction type. An instruction requesting a memory reference is decoded. The decoded instruction is then dispatched to a memory ordering unit. The instruction is retired from a load buffer and is executed after retiring.

摘要翻译： 本发明公开了一种实现高级加载指令类型的方法和装置。 解码请求存储器参考的指令。 然后将解码的指令分派到存储器订购单元。 该指令从加载缓冲区中退出，并在退出后执行。

公开(公告)号：US06205520B1

公开(公告)日：2001-03-20

申请号：US09053387

申请日：1998-03-31

申请人： Salvador Palanca ,  Vladimir Pentkovski ,  Steve Tsai ,  Subramaniam Maiyuran

发明人： Salvador Palanca ,  Vladimir Pentkovski ,  Steve Tsai ,  Subramaniam Maiyuran

IPC分类号： G06F1200

CPC分类号： G06F9/3824 ,  G06F9/3842 ,  G06F12/0804 ,  G06F12/0888 ,  G06F12/0897

摘要： A processor is disclosed. The processor includes a decoder to decode instructions and a circuit, in response to a decoded instruction, detects an incoming write back or write through streaming store instruction that misses a cache and allocates a buffer in write combining mode. The circuit, in response to a second decoded instruction, detects either an uncacheable speculative write combining store instruction or a second write back streaming store or write through streaming store instruction that hits the buffer and merges the second decoded instruction with the buffer.

摘要翻译： 公开了一种处理器。 处理器包括解码器，用于对指令和电路进行解码，响应于解码的指令，通过错过高速缓冲存储器的流存储指令检测进入写回或写入，并以写入合并模式分配缓冲器。 响应于第二解码指令，该电路检测不可缓存的推测写入组合存储指令或第二回写流存储器，或通过命中缓冲器的流存储指令进行写入，并将第二解码指令与缓冲器合并。

公开(公告)号：US06202129B1

公开(公告)日：2001-03-13

申请号：US09053386

申请日：1998-03-31

申请人： Salvador Palanca ,  Niranjan L. Cooray ,  Angad Narang ,  Vladimir Pentkovski ,  Steve Tsai

发明人： Salvador Palanca ,  Niranjan L. Cooray ,  Angad Narang ,  Vladimir Pentkovski ,  Steve Tsai

IPC分类号： G06F1200

CPC分类号： G06F12/0875 ,  G06F12/0862 ,  G06F12/0864 ,  G06F12/126

摘要： A method and system for providing cache memory management. The system comprises a main memory, a processor coupled to the main memory, and at least one cache memory coupled to the processor for caching of data. The at least one cache memory has at least two cache ways, each comprising a plurality of sets. Each of the plurality of sets has a bit which indicates whether one of the at least two cache ways contains non-temporal data. The processor accesses data from one of the main memory or the at least one cache memory.

摘要翻译： 一种用于提供高速缓存存储器管理的方法和系统。 该系统包括主存储器，耦合到主存储器的处理器以及耦合到处理器的用于数据缓存的至少一个高速缓冲存储器。 至少一个高速缓冲存储器具有至少两个高速缓存路径，每个高速缓存路径包括多个集合。 多个集合中的每一个具有指示所述至少两个高速缓存路径中的一个是否包含非时间数据的位。 处理器从主存储器或至少一个高速缓冲存储器之一访问数据。

公开(公告)号：US09383998B2

公开(公告)日：2016-07-05

申请号：US13440096

申请日：2012-04-05

申请人： Salvador Palanca ,  Stephen A. Fischer ,  Subramaniam Maiyuran ,  Shekoufeh Qawami

发明人： Salvador Palanca ,  Stephen A. Fischer ,  Subramaniam Maiyuran ,  Shekoufeh Qawami

IPC分类号： G06F15/00 ,  G06F9/30 ,  G06F9/40 ,  G06F9/38

CPC分类号： G06F9/3836 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/3012 ,  G06F9/30145 ,  G06F9/3808 ,  G06F9/3812 ,  G06F9/3834 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3867 ,  G06F2009/45583 ,  G06F2009/45591

摘要： A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.

公开(公告)号：US20050097277A1

公开(公告)日：2005-05-05

申请号：US11000054

申请日：2004-12-01

申请人： Subramaniam Maiyuran ,  Lyman Moulton ,  Salvador Palanca ,  Satish Damaraju

发明人： Subramaniam Maiyuran ,  Lyman Moulton ,  Salvador Palanca ,  Satish Damaraju

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0864 ,  G06F12/0846 ,  G06F2212/1028 ,  Y02D10/13

摘要： In a processor cache, cache circuits are mapped into one or more logical modules. Each module may be powered down independently of other modules in response to microinstructions processed by the cache. Power control may be applied on a microinstruction-by-microinstruction basis. Because the microinstructions determine which modules are used, power savings may be achieved by powering down those modules that are not used. A cache layout organization may be modified to distribute a limited number of ways across addressable cache banks. By associating fewer than a total number of ways to a bank (for example, one or two ways), the size of memory clusters within the bank may be reduced. The reduction in this size of the memory cluster contributes reduces the power needed for an address decoder to address sets within the bank.

摘要翻译： 在处理器高速缓存中，高速缓存电路被映射到一个或多个逻辑模块中。 响应于由高速缓存处理的微指令，每个模块可以独立于其它模块被关闭。 功率控制可以在微指令的基础上应用。 因为微指令决定了哪些模块被使用，所以可以通过关闭那些未使用的模块来实现功率节省。 可以修改高速缓存布局组织以在可寻址缓存组中分布有限数量的方式。 通过将小于总数量的方式与银行相关联（例如，一种或两种方式），可以减少银行内的存储器簇的大小。 存储器簇的这种尺寸的减小有助于减少地址解码器对存储体内的集合进行寻址所需的功率。