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    FAILURE INDICATOR PREDICTOR (FIP)
    1.
    发明申请
    FAILURE INDICATOR PREDICTOR (FIP) 审中-公开

    公开(公告)号：US20190043602A1

    公开(公告)日：2019-02-07

    申请号：US16112574

    申请日：2018-08-24

    申请人： Pavel Poliakov ,  Andrey Kudryavtsev ,  Shekoufeh Qawami ,  Amirali Khatib Zadeh

    发明人： Pavel Poliakov ,  Andrey Kudryavtsev ,  Shekoufeh Qawami ,  Amirali Khatib Zadeh

    IPC分类号： G11C29/38 ,  G11C29/44

    摘要： A memory controller includes a memory to store results of a reference performance test (RT) performed on a non-volatile memory (NVM) die, where the results of the RT include one or more first indicators of failure associated with one or more first read/write cycles of the NVM die before the NVM die is placed in use. The memory controller further includes an analyzer coupled with the memory to perform, in one or more second read/write cycles, one or more field tests that provide second indicators of failure associated with one or more second read/write cycles of the NVM die during the use of the NVM die, and further to predict and dynamically adjust, over one or more second read/write cycles, at least one of likelihood or expected time of failure of the NVM, based at least in part on the first and second indicators of failure.

    Flexible selection command for non-volatile memory
    5.
    发明申请
    Flexible selection command for non-volatile memory 有权
    非易失性存储器的灵活选择命令

    公开(公告)号：US20080155204A1

    公开(公告)日：2008-06-26

    申请号：US11644630

    申请日：2006-12-21

    申请人： Shekoufeh Qawami ,  Rodney R. Rozman ,  Sean S. Eilert

    发明人： Shekoufeh Qawami ,  Rodney R. Rozman ,  Sean S. Eilert

    IPC分类号： G06F13/16

    CPC分类号： G06F13/4234

    摘要： Some embodiments of the invention pertain to a memory system containing multiple memory devices, in which one or multiple ones of the memory devices may flexibly be selected at one time for a common operation to be performed by all the selected devices concurrently.

    摘要翻译： 本发明的一些实施例涉及包含多个存储器设备的存储器系统，其中存储器设备中的一个或多个存储器设备可以一次灵活地选择，以便所有所选择的设备同时执行公共操作。

    INTERFACE FOR STORAGE DEVICE ACCESS OVER MEMORY BUS
    8.
    发明申请
    INTERFACE FOR STORAGE DEVICE ACCESS OVER MEMORY BUS 有权
    用于存储器存储器的接口通过存储器总线访问

    公开(公告)号：US20150269100A1

    公开(公告)日：2015-09-24

    申请号：US14731183

    申请日：2015-06-04

    申请人： Shekoufeh Qawami ,  Rajesh Sundaram ,  David J. Zimmerman ,  Robert W. Faber

    发明人： Shekoufeh Qawami ,  Rajesh Sundaram ,  David J. Zimmerman ,  Robert W. Faber

    IPC分类号： G06F13/28 ,  G06F12/02 ,  G06F13/42 ,  G11C7/22 ,  G06F1/12 ,  G06F13/16

    CPC分类号： G06F13/28 ,  G06F1/12 ,  G06F12/0246 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/385 ,  G06F13/409 ,  G06F13/42 ,  G06F2212/7201 ,  G06F2212/7203 ,  G11C7/222 ,  H04L5/00 ,  H04L7/00 ,  Y02D10/14 ,  Y02D10/151

    摘要： A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.

    摘要翻译： 通过存储器总线访问非易失性存储器或存储器件。 存储器总线具有通常用于易失性存储器件的电接口。 耦合到总线的控制器向非易失性存储器件发送同步数据访问命令，并且基于来自非易失性存储器件的回复的期望定时从设备总线读取响应。 控制器基于何时发送命令和非易失性存储器件的特性来确定预期时序。 控制器可能不需要存储器总线上可用的所有电信号线，并且可以通过不同的电信号线组向不同组的非易失性存储器件发出数据访问命令。 存储器总线可以可用并且被配置用于与存储器控制器和易失性存储器设备或存储控制器和非易失性存储器设备一起使用。