公开(公告)号：US20060172472A1

公开(公告)日：2006-08-03

申请号：US11395434

申请日：2006-03-30

Applicant: Jeong-Young Lee ,  Se-Hwam Yu ,  Sang-Jin Jeon ,  Min-Wook Park

Inventor： Jeong-Young Lee ,  Se-Hwam Yu ,  Sang-Jin Jeon ,  Min-Wook Park

IPC: H01L29/04 ,  H01L21/84

CPC classification number: H01L27/12 ,  G02F1/13458 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136231 ,  G02F2001/13629 ,  H01L27/124 ,  H01L27/1288

Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

Abstract translation: 提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在所述下导电膜的第一部分上形成像素电极; 去除下导电膜的第二部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。

公开(公告)号：US20060103410A1

公开(公告)日：2006-05-18

申请号：US11217591

申请日：2005-08-31

Applicant: Sang-Jin Jeon

Inventor： Sang-Jin Jeon

IPC: G01R31/00

CPC classification number: G09G3/006

Abstract: A panel for a display device includes a display area and a peripheral area. The display area comprises a plurality of pixels each comprising a switching element and gate lines and data lines connected to the pixels. The peripheral area comprises a plurality of gate driving integrated circuit regions, a plurality of data driving integrated circuit regions, a plurality of repair lines disposed along the edge of the panel, connecting pads connected to both ends of the repair lines, a test line connected to at least one connecting pad, and a test pad connected to the test line. A test method for detecting disconnection of the data lines is also provided.

公开(公告)号：US20050082535A1

公开(公告)日：2005-04-21

申请号：US10926719

申请日：2004-08-26

Applicant: Min-Wook Park ,  Sang-Jin Jeon ,  Jung-Joon Park ,  Jeong-Young Lee ,  Bum-Ki Baek ,  Se-Hwan Yu ,  Sang-Ki Kwak ,  Han-Ju Lee ,  Kwon-Young Choi

Inventor： Min-Wook Park ,  Sang-Jin Jeon ,  Jung-Joon Park ,  Jeong-Young Lee ,  Bum-Ki Baek ,  Se-Hwan Yu ,  Sang-Ki Kwak ,  Han-Ju Lee ,  Kwon-Young Choi

IPC: G02F1/136 ,  G02F1/133 ,  G02F1/1339 ,  G02F1/1368 ,  G03C1/85 ,  G03C5/00 ,  G09F9/30 ,  H01L21/00 ,  H01L21/336 ,  H01L29/786

CPC classification number: G02F1/1368 ,  G02F1/1339

Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

Abstract translation: 提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在下导电膜的第一和第二部分上形成像素电极和一对冗余电极，所述冗余电极暴露下导电膜的第二部分的一部分; 去除下导电膜的第二部分的暴露部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。

公开(公告)号：US20050030440A1

公开(公告)日：2005-02-10

申请号：US10884083

申请日：2004-07-01

Applicant: Jeong-Young Lee ,  Se-Hwan Yu ,  Sang-Jin Jeon ,  Min-Wook Park

Inventor： Jeong-Young Lee ,  Se-Hwan Yu ,  Sang-Jin Jeon ,  Min-Wook Park

IPC: G02F1/13 ,  G02F1/1339 ,  G02F1/1362 ,  G02F1/1368 ,  G09F9/30 ,  H01L21/28 ,  H01L21/3205 ,  H01L23/52 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  G02F1/136

CPC classification number: H01L27/12 ,  G02F1/13458 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136231 ,  G02F2001/13629 ,  H01L27/124 ,  H01L27/1288

Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

Abstract translation: 提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在所述下导电膜的第一部分上形成像素电极; 去除下导电膜的第二部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。

公开(公告)号：US20140309387A1

公开(公告)日：2014-10-16

申请号：US14112849

申请日：2012-08-24

Applicant: Won-Hee Kim ,  Kyung-Seop Noh ,  Nan-Young Lee ,  Sang-Jin Jeon

Inventor： Won-Hee Kim ,  Kyung-Seop Noh ,  Nan-Young Lee ,  Sang-Jin Jeon

IPC: C08F4/76

CPC classification number: C08F4/76 ,  B01J21/06 ,  C08F4/64 ,  C08F4/659 ,  C08F10/00 ,  C08F4/64141 ,  C08F4/65908 ,  C08F210/16 ,  C08F210/14 ,  C08F2500/03

Abstract: The present invention relates to a transition metal catalyst composition which can exhibit high reactivity in a polymerization reaction of a polyolefin and can easily control characteristics such as chemical structure, molecular weight distribution, mechanical properties, and the like of a synthesized polyolefin, and a method of preparing a polyolefin using the catalyst composition.

Abstract translation: 本发明涉及能够在聚烯烃的聚合反应中表现出高反应性的过渡金属催化剂组合物，并且可以容易地控制合成聚烯烃的化学结构，分子量分布，机械性能等特性，以及方法 使用该催化剂组合物制备聚烯烃。

公开(公告)号：US08575617B2

公开(公告)日：2013-11-05

申请号：US13465855

申请日：2012-05-07

Applicant: Gwang-Bum Ko ,  Sang Jin Jeon

Inventor： Gwang-Bum Ko ,  Sang Jin Jeon

IPC: H01L29/04 ,  H01L29/15 ,  H01L31/036 ,  H01L29/10 ,  H01L31/0376 ,  H01L31/20

CPC classification number: H01L27/124 ,  H01L22/14 ,  H01L22/34

Abstract: A thin film transistor array panel and a manufacturing method therefor. A shorting bar for connecting a thin film transistor with data lines is formed separate from the data lines, and then the data lines and the shorting bar are connected through a connecting member. As a result, all the data lines are floated during manufacture, so that variation in etching speed between data lines does not occur. Since variation in etching speed between the data lines can be prevented, performance deterioration of the transistor caused by a thickness difference in the lower layer of the data line can be prevented, as can resulting deterioration in display quality. Also, the influence of static electricity can be reduced or eliminated. Furthermore, since the data lines and the shorting bar are connected to each other, the generation of static electricity can be prevented or reduced, and quality testing is more readily performed.

Abstract translation: 一种薄膜晶体管阵列面板及其制造方法。 与数据线连接薄膜晶体管的短路棒与数据线分开形成，然后通过连接部件连接数据线和短路棒。 结果，在制造期间所有的数据线都浮起来，从而不会发生数据线之间蚀刻速度的变化。 由于可以防止数据线之间的蚀刻速度的变化，可以防止由数据线的下层的厚度差导致的晶体管的性能劣化，这可能导致显示质量的劣化。 此外，可以减少或消除静电的影响。 此外，由于数据线和短路棒彼此连接，所以可以防止或减少静电的产生，并且更易于进行质量测试。

公开(公告)号：US07692443B2

公开(公告)日：2010-04-06

申请号：US11563248

申请日：2006-11-27

Applicant: Sang Jin Jeon

Inventor： Sang Jin Jeon

IPC: G01R31/00

CPC classification number: G09G3/006 ,  G02F2001/136254 ,  G09G3/3406 ,  G09G2300/04

Abstract: A display substrate includes a plurality of gate lines, a plurality of data lines, a gate signal-inputting unit, a first test unit, and a first dummy switching unit. The gate lines extend in a first direction. The data lines extend in a second direction intersected with the first direction. The gate signal-inputting unit is formed at a first end of each of the gate lines to apply gate signals to the gate lines. The first test unit is formed at a second end of each of the gate lines opposite to the first end applying a first test signal to the gate lines. The first dummy switching unit is formed between the gate signal-inputting unit and the first test unit and transferring the first test signal to the gate lines.

Abstract translation: 显示基板包括多条栅极线，多条数据线，栅极信号输入单元，第一测试单元和第一虚拟开关单元。 栅极线在第一方向上延伸。 数据线在与第一方向相交的第二方向上延伸。 栅极信号输入单元形成在每条栅极线的第一端，以将栅极信号施加到栅极线。 第一测试单元形成在与第一端相对的每个栅极线的第二端，向栅极线施加第一测试信号。 第一虚拟开关单元形成在栅极信号输入单元和第一测试单元之间，并将第一测试信号传送到栅极线。

公开(公告)号：US20080211760A1

公开(公告)日：2008-09-04

申请号：US11932532

申请日：2007-10-31

Applicant: Seung-Soo Baek ,  Yong Soon Lee ,  Min Cheol Lee ,  Young Bum Kim ,  Sang Jin Jeon

Inventor： Seung-Soo Baek ,  Yong Soon Lee ,  Min Cheol Lee ,  Young Bum Kim ,  Sang Jin Jeon

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G2310/0286 ,  G09G2320/0223 ,  G11C19/184

Abstract: A liquid crystal display and a dual gate driving circuit therefor wherein the number of signal lines are reduced by sharing a start pulse and an output signal of a dummy stage. The liquid crystal display includes a timing controller generating an output enable signal, a gate clock, and a signal start signal in response to an external input signal, a level shifter generating a gate clock pulse and a gate clock bar pulse in response to the output enable signal and the gate clock and generating a single start pulse in response to the start signal and the gate clock, and first and second gate driving circuits outputting the gate clock pulse or the gate clock bar pulse as a gate driving signal to the plurality of gate lines in response to the single start pulse.

Abstract translation: 一种液晶显示器及其双栅极驱动电路，其中通过共享虚拟级的起始脉冲和输出信号来减少信号线的数量。 液晶显示器包括响应于外部输入信号产生输出使能信号，门时钟和信号起始信号的定时控制器，响应于输出产生栅极时钟脉冲和栅极时钟脉冲脉冲的电平转换器 使能信号和栅极时钟，并且响应于起始信号和栅极时钟产生单个起始脉冲，并且第一和第二栅极驱动电路将栅极时钟脉冲或栅极时钟条脉冲作为栅极驱动信号输出到多个 响应于单个起始脉冲的栅极线。

公开(公告)号：US20080093600A1

公开(公告)日：2008-04-24

申请号：US11958230

申请日：2007-12-17

Applicant: Min-Wook PARK ,  Bum-Ki Baek ,  Jeong-Young Lee ,  Kwon-Young Choi ,  Sang-Ki Kwak ,  Sang-Jin Jeon

Inventor： Min-Wook PARK ,  Bum-Ki Baek ,  Jeong-Young Lee ,  Kwon-Young Choi ,  Sang-Ki Kwak ,  Sang-Jin Jeon

IPC: H01L29/04

CPC classification number: H01L29/41733 ,  H01L27/124

Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

Abstract translation: 提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在所述下导电膜的第一部分上形成像素电极; 去除下导电膜的第二部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。

公开(公告)号：US07358123B2

公开(公告)日：2008-04-15

申请号：US11395434

申请日：2006-03-30

Applicant: Jeong-Young Lee ,  Se-Hwan Yu ,  Sang-Jin Jeon ,  Min-Wook Park

Inventor： Jeong-Young Lee ,  Se-Hwan Yu ,  Sang-Jin Jeon ,  Min-Wook Park

IPC: H01L21/00

CPC classification number: H01L27/12 ,  G02F1/13458 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136231 ,  G02F2001/13629 ,  H01L27/124 ,  H01L27/1288

Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

Abstract translation: 提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在所述下导电膜的第一部分上形成像素电极; 去除下导电膜的第二部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。