公开(公告)号：US07015077B1

公开(公告)日：2006-03-21

申请号：US10970085

申请日：2004-10-21

Applicant: Andrew Horch ,  Scott Robins

Inventor： Andrew Horch ,  Scott Robins

IPC: H01L21/332

CPC classification number: H01L29/74 ,  H01L21/76224 ,  H01L21/763 ,  H01L27/0817 ,  H01L29/0649

Abstract: A semiconductor device is formed having a thyristor and trench arranged to electrically insulate an emitter region of the thyristor from another circuit structure. In one example embodiment of the present invention, a trench having a bottom portion with two different trench depths is etched in the substrate. A thyristor is formed having a control port in a trench and having an emitter region adjacent to the trench and below an upper surface of the substrate. A deeper portion of the trench electrically insulates the emitter region from the other circuit structure. The control port is capacitively coupled to the thyristor and to the other circuit structure (e.g., in response to at least one edge of a voltage pulse applied thereto). In one implementation, the trench further includes an emitter-access connector extending from the emitter region to an upper surface of the substrate. These approaches are also useful in high-density circuit applications, such as memory applications, where the semiconductor device is formed in close proximity with other circuitry, such as with other thyristors. In addition, the isolation approach is useful for applications where a cathode-down thyristor is used, such as when it is desirable to form the thyristor control port near a bottom portion of the thyristor. Moreover, the approaches discussed herein are useful for electrically isolating various portions of the semiconductor device using a relatively limited number of etching steps.

Abstract translation: 形成半导体器件，其具有晶闸管和沟槽，其布置成将晶闸管的发射极区域与另一个电路结构电绝缘。 在本发明的一个示例性实施例中，在衬底中蚀刻具有具有两个不同沟槽深度的底部的沟槽。 晶闸管形成为具有沟槽中的控制端口，并且具有与沟槽相邻的发射极区域以及衬底的上表面下方。 沟槽的较深部分将发射极区域与另一个电路结构电绝缘。 控制端口电容耦合到晶闸管和另一电路结构（例如，响应于施加到晶闸管的电压脉冲的至少一个边缘）。 在一个实施方式中，沟槽还包括从发射极区延伸到衬底的上表面的发射器 - 接入连接器。 这些方法在诸如存储器应用的高密度电路应用中也是有用的，其中半导体器件形成在与其它电路（例如与其他晶闸管）相近的位置。 此外，隔离方法对于使用阴极 - 下降晶闸管的应用是有用的，例如当期望在晶闸管的底部附近形成晶闸管控制端口时。 此外，本文讨论的方法可用于使用相对有限数量的蚀刻步骤电绝缘半导体器件的各个部分。

公开(公告)号：US06911680B1

公开(公告)日：2005-06-28

申请号：US10890031

申请日：2004-07-13

Applicant: Andrew Horch ,  Scott Robins ,  Farid Nemati

Inventor： Andrew Horch ,  Scott Robins ,  Farid Nemati

IPC: H01L21/331 ,  H01L27/11 ,  H01L29/74 ,  H01L29/745

CPC classification number: H01L29/66242 ,  H01L27/11 ,  H01L29/7436 ,  H01L29/7455

Abstract: A semiconductor memory device having a thyristor is manufactured in a manner that makes possible self-alignment of one or more portions of the thyristor. According to an example embodiment of the present invention, a gate is formed over a first portion of doped substrate. The gate is used to mask a portion of the doped substrate and a second portion of the substrate is doped before or after a spacer is formed. After the second portion of the substrate is doped, the spacer is then formed adjacent to the gate and used to mask the second portion of the substrate while a third portion of the substrate is doped. The gate and spacer are thus used to form self-aligned doped portions of the substrate, wherein the first and second portions form base regions and the third portion form an emitter region of a thyristor. In another implementation, the spacer is also adapted to prevent formation of salicide on the portion of the thyristor beneath the spacer, self-aligning the salicide to the junction between the second and third portions. In addition, dimensions such as width and other characteristics of the doped portions that are used to form a thyristor can be controlled without necessarily using a separate mask.

Abstract translation: 制造具有晶闸管的半导体存储器件以能够使晶闸管的一个或多个部分自对准的方式。 根据本发明的示例性实施例，在掺杂衬底的第一部分上形成栅极。 栅极用于掩模掺杂衬底的一部分，并且衬底的第二部分在形成间隔物之前或之后被掺杂。 在衬底的第二部分被掺杂之后，然后在衬底的第三部分被掺杂的同时，将衬底形成为邻近栅极并用于掩蔽衬底的第二部分。 因此，栅极和间隔物用于形成衬底的自对准掺杂部分，其中第一和第二部分形成基极区，第三部分形成晶闸管的发射极区。 在另一实施方案中，间隔物还适于防止在间隔物下方的可控硅部分上形成自对准硅化物，使自对准硅化物与第二和第三部分之间的连接处。 此外，可以控制用于形成晶闸管的掺杂部分的宽度和其它特性的尺寸，而不必使用单独的掩模。

公开(公告)号：US06891205B1

公开(公告)日：2005-05-10

申请号：US10666220

申请日：2003-09-19

Applicant: Hyun-Jin Cho ,  Farid Nemati ,  Scott Robins

Inventor： Hyun-Jin Cho ,  Farid Nemati ,  Scott Robins

IPC: G11C11/39 ,  H01L29/74 ,  H01L29/749

CPC classification number: H01L29/749 ,  G11C11/39 ,  H01L29/7436

Abstract: A semiconductor device having a thyristor-based memory device exhibits improved stability under adverse operating conditions related to temperature, noise, electrical disturbances and light. In one particular example embodiment of the present invention, a semiconductor device includes a thyristor-based memory device that uses a shunt that effects a leakage current in the thyristor. The thyristor includes a capacitively-coupled control port and anode and cathode end portions. Each of the end portions has an emitter region and an adjacent base region. In one implementation, the current shunt is located between the emitter and base region of one of the end portions of the thyristor and is configured and arranged to shunt low-level current therebetween. In connection with an example embodiment, it has been discovered that shunting current in this manner improves the ability of the device to operate under adverse conditions that would, absent the shunt, result in inadvertent turn on, while keeping the standby current of the memory device to an acceptably low level.

Abstract translation: 具有基于晶闸管的存储器件的半导体器件在与温度，噪声，电扰动和光线相关的不利操作条件下表现出改进的稳定性。 在本发明的一个具体示例实施例中，半导体器件包括基于晶闸管的存储器件，其使用在晶闸管中产生漏电流的分流器。 晶闸管包括电容耦合控制端口和阳极和阴极端部分。 每个端部具有发射极区域和相邻的基极区域。 在一个实施方案中，电流分流器位于晶闸管的一个端部的发射极和基极区域之间，并且被配置和布置成在它们之间分流低电平电流。 结合示例性实施例，已经发现，以这种方式分流电流提高了器件在不利条件下操作的能力，这种不利条件将在不存在分流的情况下导致无意中导通，同时保持存储器件的待机电流 达到可接受的低水平。

公开(公告)号：US06888177B1

公开(公告)日：2005-05-03

申请号：US10253350

申请日：2002-09-24

Applicant: Farid Nemati ,  Scott Robins ,  Andrew Horch

Inventor： Farid Nemati ,  Scott Robins ,  Andrew Horch

IPC: H01L21/332 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12 ,  H01L29/417 ,  H01L29/74

CPC classification number: H01L27/108 ,  H01L21/84 ,  H01L23/535 ,  H01L27/1203 ,  H01L29/41716 ,  H01L29/66393 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A thyristor-based semiconductor device exhibits a relatively increased base-emitter capacitance. According to an example embodiment of the present invention, the junction area between a base region and an adjacent emitter region of a thyristor is increased, relative to the junction area between other regions in the thyristor. In one implementation, the base region is formed extending on two sides of the emitter region. In another implementation, the thyristor is formed on a buried insulator layer of a silicon-on-insulator (SOI) structure, with the base region having a first portion laterally adjacent to the emitter region and having a second portion between the emitter region and the buried insulator.

Abstract translation: 基于晶闸管的半导体器件表现出相对增加的基极 - 发射极电容。 根据本发明的示例性实施例，晶闸管的基极区域和相邻发射极区域之间的结面积相对于晶闸管中的其它区域之间的接合面积增加。 在一个实施方式中，形成在发射极区域的两侧上延伸的基极区域。 在另一种实施方式中，晶闸管形成在绝缘体上硅（SOI）结构的掩埋绝缘体层上，其中基极区域具有与发射极区域相邻的第一部分，并且在发射极区域和发射极区域之间具有第二部分 埋绝缘体。

公开(公告)号：US06815734B1

公开(公告)日：2004-11-09

申请号：US10262758

申请日：2002-10-01

Applicant: Andrew Horch ,  Scott Robins

Inventor： Andrew Horch ,  Scott Robins

IPC: H01L2974

CPC classification number: H01L29/74 ,  H01L21/76224 ,  H01L21/763 ,  H01L27/0817 ,  H01L29/0649

Abstract: A semiconductor device is formed having a thyristor and trench arranged to electrically insulate an emitter region of the thyristor from another circuit structure. In one example embodiment of the present invention, a trench having a bottom portion with two different trench depths is etched in the substrate. A thyristor is formed having a control port in a trench and having an emitter region adjacent to the trench and below an upper surface of the substrate. A deeper portion of the trench electrically insulates the emitter region from the other circuit structure. The control port is capacitively coupled to the thyristor and to the other circuit structure (e.g. in response to at least one edge of a voltage pulse applied thereto). In one implementation, the trench further includes an emitter-access connector extending from the emitter region to an upper surface of the substrate. These approaches are also useful in high-density circuit applications, such as memory applications, where the semiconductor device is formed in close proximity with other circuitry, such as with other thyristors. In addition, the isolation approach is useful for applications where a cathode-down thyristor is used, such as when it is desirable to form the thyristor control port near a bottom portion of the thyristor. Moreover, the approaches discussed herein are useful for electrically isolating various portions of the semiconductor device using a relatively limited number of etching steps.

Abstract translation: 形成半导体器件，其具有晶闸管和沟槽，其布置成将晶闸管的发射极区域与另一个电路结构电绝缘。 在本发明的一个示例性实施例中，在衬底中蚀刻具有具有两个不同沟槽深度的底部的沟槽。 晶闸管形成为具有沟槽中的控制端口，并且具有与沟槽相邻的发射极区域以及衬底的上表面下方。 沟槽的较深部分将发射极区域与另一个电路结构电绝缘。 控制端口电容耦合到晶闸管和另一个电路结构（例如响应于施加到晶闸管的电压脉冲的至少一个边缘）。 在一个实施方式中，沟槽还包括从发射极区延伸到衬底的上表面的发射器 - 接入连接器。 这些方法在诸如存储器应用的高密度电路应用中也是有用的，其中半导体器件形成在与其它电路（例如与其他晶闸管）相近的位置。 此外，隔离方法对于使用阴极 - 下降晶闸管的应用是有用的，例如当期望在晶闸管的底部附近形成晶闸管控制端口时。 此外，本文讨论的方法可用于使用相对有限数量的蚀刻步骤电绝缘半导体器件的各个部分。

公开(公告)号：US06777271B1

公开(公告)日：2004-08-17

申请号：US10201654

申请日：2002-07-23

Applicant: Scott Robins ,  Andrew Horch ,  Farid Nemati ,  Hyun-Jin Cho

Inventor： Scott Robins ,  Andrew Horch ,  Farid Nemati ,  Hyun-Jin Cho

IPC: H01L21332

CPC classification number: H01L29/66363 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/763 ,  H01L27/0617 ,  H01L27/0817

Abstract: A semiconductor device includes a thyristor designed to reduce or eliminate manufacturing and operational difficulties commonly experienced in the formation and operation of NDR devices. According to one example embodiment of the present invention, the semiconductor substrate is trenched adjacent a doped or dopable substrate region, which is formed to included at least two vertically-adjacent thyristor regions of different polarity. A capacitively-coupled control port for the thyristor is coupled to at least one of the thyristor regions. The trench also includes a dielectric material for electrically insulating the vertically-adjacent thyristor regions. The thyristor is electrically connected to other circuitry in the device, such as a transistor, and used to form a device, such as a memory cell.

Abstract translation: 半导体器件包括设计用于减少或消除在NDR器件的形成和操作中通常经历的制造和操作困难的晶闸管。 根据本发明的一个示例实施例，半导体衬底在掺杂或可掺杂的衬底区域附近被沟槽，该衬底区域形成为包括不同极性的至少两个垂直相邻的晶闸管区域。 用于晶闸管的电容耦合控制端口耦合到至少一个晶闸管区域。 沟槽还包括用于使垂直相邻的晶闸管区域电绝缘的电介质材料。 晶闸管电连接到器件中的其它电路，例如晶体管，并用于形成诸如存储器单元的器件。

公开(公告)号：US06683330B1

公开(公告)日：2004-01-27

申请号：US10262697

申请日：2002-10-01

Applicant: Andrew Horch ,  Scott Robins

Inventor： Andrew Horch ,  Scott Robins

IPC: H01L2974

CPC classification number: H01L21/76224 ,  H01L27/0817 ,  H01L29/74

Abstract: A semiconductor device is formed including a substrate having an upper surface, a thyristor region in the substrate and a control port adapted for capacitively coupling to at least a portion of the thyristor region via a dielectric material. According to an example embodiment of the present invention, a trench is formed in the substrate and subsequently filled with materials including dielectric material and a control port. The control port is adapted for capacitively coupling to the thyristor via the dielectric material for controlling current flow in the thyristor (e.g., for causing an outflow of minority carriers from a portion of the thyristor for switching the thyristor from conducting state to a blocking state). A portion of the substrate adjacent to the upper surface is implanted with a species of ions, and the dielectric material via which the control port capacitively couples to the thyristor does not include the species of ions. In one implementation, a filled portion of the trench over the control port inhibits ions from implanting the dielectric material. In another implementation, the control port is formed recessed, relative to the upper surface of the substrate, such that the ion implant depth of the region adjacent to the upper surface is shallower than the recessed control port. With this approach, current control in the thyristor is effected using an arrangement that inhibits ion implantation damage to dielectric material used for controlling current in the thyristor.

Abstract translation: 形成半导体器件，其包括具有上表面的衬底，衬底中的晶闸管区域和适于经由电介质材料电容耦合到晶闸管区域的至少一部分的控制端口。 根据本发明的示例性实施例，在衬底中形成沟槽，随后填充包括电介质材料和控制端口的材料。 控制端口适于通过用于控制晶闸管中的电流的电介质材料电容耦合到晶闸管（例如，用于使晶闸管的一部分的少数载流子流出，将晶闸管从导通状态切换到阻塞状态） 。 与上表面相邻的衬底的一部分注入一些离子，并且电容耦合到晶闸管的电介质材料不包括离子种类。 在一个实施方案中，控制端口上的沟槽的填充部分抑制离子注入电介质材料。 在另一实施方案中，控制端口相对于衬底的上表面形成为凹陷，使得与上表面相邻的区域的离子注入深度比凹入的控制端口浅。 采用这种方法，晶闸管的电流控制是通过抑制用于控制晶闸管中的电流的电介质材料的离子注入损伤的装置实现的。

公开(公告)号：US07491586B2

公开(公告)日：2009-02-17

申请号：US11159514

申请日：2005-06-22

Applicant: Andrew E Horch ,  Hyun-Jin Cho ,  Farid Nemati ,  Scott Robins ,  Rajesh N. Gupta ,  Kevin J. Yang

Inventor： Andrew E Horch ,  Hyun-Jin Cho ,  Farid Nemati ,  Scott Robins ,  Rajesh N. Gupta ,  Kevin J. Yang

IPC: H01L21/332 ,  H01L21/04 ,  H01L21/425

CPC classification number: G11C11/39 ,  H01L27/0817 ,  H01L29/7436 ,  H01L29/7455 ,  H01L29/749

Abstract: A method of fabricating a thyristor-based memory may include forming different opposite conductivity-type regions in silicon for defining a thyristor and an access device in series relationship. An activation anneal may activate dopants previously implanted for the different regions. A damaging implant of germanium or xenon or argon may be directed into select regions of the silicon including at least one p-n junction region for the access device and the thyristor. A re-crystallization anneal may then be performed to re-crystallize at least some of the damaged lattice structure resulting from the damaging implant. The re-crystallization anneal may use a temperature less than that of the previous activation anneal.

Abstract translation: 制造基于晶闸管的存储器的方法可以包括在硅中形成用于限定可控硅和串联连接的存取装置的不同的相反导电型区域。 激活退火可以激活先前为不同区域植入的掺杂剂。 可以将锗或氙或氩的有害植入物引导到硅的选择区域中，包括用于进入装置和晶闸管的至少一个p-n结区域。 然后可以进行重结晶退火，以重新结晶由损伤性植入物引起的至少一些损伤的晶格结构。 再结晶退火可以使用比先前激活退火的温度低的温度。

公开(公告)号：US07489008B1

公开(公告)日：2009-02-10

申请号：US11522037

申请日：2006-09-16

Applicant: Zachary K. Lee ,  Farid Nemati ,  Scott Robins

Inventor： Zachary K. Lee ,  Farid Nemati ,  Scott Robins

IPC: H10L27/12

CPC classification number: H01L27/1203 ,  H01L29/7841

Abstract: A semiconductor device may comprise a partially-depleted SOI MOSFET having a floating body region disposed between a source and drain. The floating body region may be driven to receive injected carriers for adjusting its potential during operation of the MOSFET. In a particular case, the MOSFET may comprise another region of semiconductor material in contiguous relationship with a drain/source region of the MOSFET and on a side thereof opposite to the body region. This additional region may be formed with a conductivity of type opposite the drain/source, and may establish an effective bipolar device per the body, the drain/source and the additional region. The geometries and doping thereof may be designed to establish a transport gain of magnitude sufficient to assist the injection of carriers into the floating body region, yet small enough to guard against inter-latching with the MOSFET.

Abstract translation: 半导体器件可以包括部分耗尽的SOI MOSFET，其具有设置在源极和漏极之间的浮体区域。 可以驱动浮体区域以接收注入的载流子，以在MOSFET的操作期间调整其电位。 在特定的情况下，MOSFET可以包括与MOSFET的漏极/源极区域和与体区域相对的一侧连续关系的半导体材料的另一区域。 该附加区域可以形成为具有与漏极/源极相反的类型的导电性，并且可以建立每个主体，漏极/源极和附加区域的有效双极器件。 其几何形状和掺杂可被设计成建立足以帮助载流子注入浮体区域的传输增益，但足够小以防止与MOSFET的互锁。

公开(公告)号：US07245525B1

公开(公告)日：2007-07-17

申请号：US11194184

申请日：2005-08-01

Applicant: Zachary K. Lee ,  Farid Nemati ,  Scott Robins

Inventor： Zachary K. Lee ,  Farid Nemati ,  Scott Robins

IPC: G11C11/00

CPC classification number: G11C11/39

Abstract: In a thyristor based memory cell, one end of a reversed-biased diode is connected to the cathode of the thyristor. During standby, the second end of the diode is biased at a voltage that is higher than that at the cathode of the thyristor. During restore operation, the second end is pulled down to zero or even a negative value. If the cell is storing a “1,” the voltage at the thyristor cathode can be approximately 0.6 volt at the time of the pull down. The large forward-bias across the diode pulls down the thryistor cathode. This causes the thyristor to be restored. If the cell is storing a “0,” the voltage at the thyristor cathode can be approximately zero volt. The small or zero forward-bias across the diode is unable to disturb the “0” state. As a result, the memory cell is restored to its original state.

Abstract translation: 在基于晶闸管的存储单元中，反向偏置二极管的一端连接到晶闸管的阴极。 在待机期间，二极管的第二端被偏置在高于晶闸管阴极处的电压。 在恢复操作期间，第二端被拉低至零或甚至负值。 如果电池正在存储“1”，则在下拉时，晶闸管阴极处的电压可能约为0.6伏特。 二极管两端的大正向偏置可降低晶闸管阴极。 这导致晶闸管恢复。 如果电池正在存储“0”，晶闸管阴极处的电压可以近似为零伏。 二极管两端的小或零正向偏置不能干扰“0”状态。 结果，存储单元恢复到其原始状态。