公开(公告)号：US08576600B2

公开(公告)日：2013-11-05

申请号：US13420038

申请日：2012-03-14

申请人： Jung Hwan Lee ,  Seong Je Park ,  Ji Hwan Kim ,  Myung Cho ,  Beom Seok Hah

发明人： Jung Hwan Lee ,  Seong Je Park ,  Ji Hwan Kim ,  Myung Cho ,  Beom Seok Hah

IPC分类号： G11C15/00

CPC分类号： G11C15/046 ,  G11C16/10

摘要： A semiconductor memory device includes a memory array configured to include memory cells for storing input data and Code Address Memory (CAM) cells for storing setting data used to set an operation condition; an operation circuit configured to perform a CAM read operation by supplying a read voltage to the CAM cells, perform a test operation for detecting unstable CAM cells in each of which a difference between a threshold voltage and the read voltage is smaller than a permitted limit, from among the CAM cells, and perform an erase operation or a program operation for the unstable CAM cells; and a controller configured to control the operation circuit so that the program operation for storing the setting data in the unstable CAM cells is performed if the number of unstable CAM cells detected in the test operation is greater than a permitted value.

摘要翻译： 半导体存储器件包括：存储器阵列，被配置为包括用于存储输入数据的存储器单元和用于存储用于设置操作条件的设置数据的代码地址存储器（CAM）单元; 配置为通过向CAM单元提供读取电压来执行CAM读取操作的操作电路，执行用于检测阈值电压和读取电压之间的差小于允许极限的不稳定的CAM单元的测试操作， 从CAM单元中进行擦除操作或对不稳定的CAM单元的编程动作; 以及控制器，其被配置为如果在测试操作中检测到​​的不稳定的CAM单元的数量大于允许值，则执行用于将设置数据存储在不稳定的CAM单元中的程序操作。

公开(公告)号：US08456907B2

公开(公告)日：2013-06-04

申请号：US13337196

申请日：2011-12-26

申请人： Ji Hwan Kim ,  Seong Je Park ,  Jung Hwan Lee ,  Myung Cho ,  Beom Seok Hah

发明人： Ji Hwan Kim ,  Seong Je Park ,  Jung Hwan Lee ,  Myung Cho ,  Beom Seok Hah

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/565

摘要： A method of operating a semiconductor memory device includes performing a first program loop including a first program operation and a first verification operation in order to store a lower bit data of n-bit data in memory cells coupled to a page, performing a subprogram loop for memory cells of an erase state, having threshold voltages lower than a target voltage of a negative potential, so that the threshold voltages of the memory cells of the erase state become higher than the target voltage, and performing a second program loop including a second program operation and a second verification operation in order to store an upper bit data of the n-bit data in the memory cells.

摘要翻译： 一种操作半导体存储器件的方法包括执行包括第一程序操作和第一验证操作的第一程序循环，以便将n位数据的低位数据存储在耦合到页面的存储单元中，执行子程序循环 具有低于负电位的目标电压的阈值电压的擦除状态的存储单元，使得擦除状态的存储单元的阈值电压变得高于目标电压，并且执行包括第二程序的第二程序循环 操作和第二验证操作，以便将n位数据的高位数据存储在存储单元中。

公开(公告)号：US20120269010A1

公开(公告)日：2012-10-25

申请号：US13238435

申请日：2011-09-21

申请人： Myung CHO ,  Seong-Je Park ,  Jung-Hwan Lee ,  Ji-Hwan Kim ,  Beom-Seok Hah

发明人： Myung CHO ,  Seong-Je Park ,  Jung-Hwan Lee ,  Ji-Hwan Kim ,  Beom-Seok Hah

IPC分类号： G11C7/06

CPC分类号： G11C11/5642 ,  G11C16/0483 ,  G11C2211/5646

摘要： A memory includes at least one first flag cell configured to store first flag data, at least one second flag cell configured to store second flag data, at least one first sensing node having a voltage level determined by the first flag data of the first flag cell, at least one second sensing having a voltage level determined by the second flag data of the second flag cell, a selection circuit configured to select the first sensing node or the second sensing node in response to a flag address; and a determination circuit having an internal node through which current corresponding to a voltage level of a selected sensing node flows and configured to determine a logic value of flag data corresponding to the selected sensing node among the first and second flag data by using an amount of current flowing through the internal node.

摘要翻译： 存储器包括被配置为存储第一标志数据的至少一个第一标志单元，被配置为存储第二标志数据的至少一个第二标志单元，具有由第一标志单元的第一标志数据确定的电压电平的至少一个第一感测节点 至少一个第二感测具有由第二标志单元的第二标志数据确定的电压电平，选择电路被配置为响应于标志地址选择第一感测节点或第二感测节点; 以及确定电路，其具有内部节点，通过所述内部节点流过与所选择的感测节点的电压电平相对应的电流，并且被配置为通过使用一定数量的第一和第二标志数据来确定与所选择的感测节点对应的标志数据的逻辑值 电流流过内部节点。

公开(公告)号：US20120218818A1

公开(公告)日：2012-08-30

申请号：US13104475

申请日：2011-05-10

申请人： Jung-Chul HAN ,  Seong-Je Park

发明人： Jung-Chul HAN ,  Seong-Je Park

IPC分类号： G11C16/10 ,  G11C16/04

CPC分类号： G11C16/3454 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10

摘要： A nonvolatile memory device includes a page region including a plurality of normal cells and a plurality of auxiliary cells, a detecting unit configured to output a pass signal when at least one cell is programmed with a voltage higher than a reference voltage among program target cells of the page region, a count storing unit configured to store a count in the plurality of auxiliary cells during a first program operation for the page region, wherein the count indicates a total number of program pulses applied to the at least one cell until the pass signal is outputted from the detecting unit, and a voltage setting unit configured to set a program start voltage for a second program operation of the page region based on the count stored in the plurality of auxiliary cells.

摘要翻译： 非易失性存储器件包括包括多个正常单元和多个辅助单元的页面区域，检测单元，被配置为当至少一个单元被编程为高于参考电压的电压时，输出通过信号， 所述页面区域，计数存储单元，被配置为在所述页面区域的第一编程操作期间在所述多个辅助单元中存储计数，其中所述计数指示施加到所述至少一个单元的编程脉冲的总数，直到所述通过信号 从所述检测单元输出，以及电压设定单元，其被配置为基于存储在所述多个辅助单元中的计数来设置用于所述页面区域的第二编程操作的程序开始电压。

公开(公告)号：US20120170366A1

公开(公告)日：2012-07-05

申请号：US13337196

申请日：2011-12-26

申请人： Ji Hwan KIM ,  Seong Je PARK ,  Jung Hwan LEE ,  Myung CHO ,  Beom Seok HAH

发明人： Ji Hwan KIM ,  Seong Je PARK ,  Jung Hwan LEE ,  Myung CHO ,  Beom Seok HAH

IPC分类号： G11C16/10 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/565

摘要： A method of operating a semiconductor memory device includes performing a first program loop including a first program operation and a first verification operation in order to store a lower bit data of n-bit data in memory cells coupled to a page, performing a subprogram loop for memory cells of an erase state, having threshold voltages lower than a target voltage of a negative potential, so that the threshold voltages of the memory cells of the erase state become higher than the target voltage, and performing a second program loop including a second program operation and a second verification operation in order to store an upper bit data of the n-bit data in the memory cells.

摘要翻译： 一种操作半导体存储器件的方法包括执行包括第一程序操作和第一验证操作的第一程序循环，以便将n位数据的低位数据存储在耦合到页面的存储单元中，执行子程序循环 具有低于负电位的目标电压的阈值电压的擦除状态的存储单元，使得擦除状态的存储单元的阈值电压变得高于目标电压，并且执行包括第二程序的第二程序循环 操作和第二验证操作，以便将n位数据的高位数据存储在存储单元中。

公开(公告)号：US20110075479A1

公开(公告)日：2011-03-31

申请号：US12962570

申请日：2010-12-07

申请人： Jin Yong Seong ,  Seong Je Park

发明人： Jin Yong Seong ,  Seong Je Park

IPC分类号： G11C16/34 ,  G11C16/04

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5642

摘要： A multi-level cell copyback program method in a non-volatile memory device is disclosed. The method includes performing a multi-level cell copyback program operation; performing selectively a first verifying operation, a second verifying operation or a third verifying operation in accordance with data stored in an MSB node of the first register or data stored in an LSB node of the second register. The first verifying operation is based on a first verifying voltage. The second verifying operation is based on a second verifying voltage higher than the first verifying voltage. And the third verifying operation is based on a third verifying voltage higher than the second verifying voltage. The copy back program operation is performed repeatedly in accordance with result of the verifying operation.

摘要翻译： 公开了一种在非易失性存储器件中的多级单元复制程序方法。 该方法包括执行多级单元复制程序操作; 根据存储在第一寄存器的MSB节点中的数据或存储在第二寄存器的LSB节点中的数据选择性地执行第一验证操作，第二验证操作或第三验证操作。 第一验证操作基于第一验证电压。 第二验证操作基于比第一验证电压高的第二验证电压。 并且第三验证操作基于比第二验证电压高的第三验证电压。 根据验证操作的结果重复执行复制回程序操作。

公开(公告)号：US07898869B2

公开(公告)日：2011-03-01

申请号：US12243644

申请日：2008-10-01

申请人： Seong Je Park

发明人： Seong Je Park

IPC分类号： G11C11/34

CPC分类号： G11C8/08 ,  G11C8/14 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/26 ,  G11C16/30

摘要： A word line voltage generator that generates a word line voltage, which is selectively changed depending on a temperature, a flash memory device including the word line voltage generator, and a method of generating the word line voltage. The word line voltage generator includes a read voltage generator and a controller. The read voltage generator generates a read voltage or a verify voltage based on one of reference voltages in response to an enable control signal and supplies the read voltage or the verify voltage to one of a plurality of global word lines in response to a row decoding signal, during a read operation or a read operation for program verification, of the flash memory device. The controller generates one of the reference voltages in response to a read control signal or a verify control signal. When a temperature is varied, the read voltage generator changes the level of the read voltage or the verify voltage in reverse proportion to the temperature.

摘要翻译： 一种字线电压发生器，其产生根据温度选择性地改变的字线电压，包括字线电压发生器的闪存器件，以及产生字线电压的方法。 字线电压发生器包括读电压发生器和控制器。 读取电压发生器响应于使能控制信号而产生基于参考电压之一的读取电压或验证电压，并响应于行解码信号将读取电压或验证电压提供给多个全局字线中的一个 ，在用于程序验证的读取操作或读取操作期间。 响应于读控制信号或验证控制信号，控制器产生参考电压之一。 当温度变化时，读取电压发生器以与温度成反比的方式改变读取电压或验证电压的电平。

公开(公告)号：US20100195400A1

公开(公告)日：2010-08-05

申请号：US12647593

申请日：2009-12-28

申请人： Kyu Hee Lim ,  Seong Je Park ,  Jung Chul Han

发明人： Kyu Hee Lim ,  Seong Je Park ,  Jung Chul Han

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2216/14

摘要： A nonvolatile memory device comprises a page buffer unit, a counter, a program pulse application number storage unit, and a program start voltage setting unit. The page buffer is configured to output a 1-bit pass signal when a cell programmed to exceed a reference voltage, from among target program cells included in a single page, exists. The counter is configured to count a number of program pulses applied to determine a program pulse application number. The program pulse application number storage unit is configured to store a number of program pulses applied until the 1-bit pass signal is received during a program operation for a first page. The program start voltage setting unit is configured to set a program start voltage for a second page based on the stored program pulse application number.

摘要翻译： 非易失性存储器件包括页缓冲器单元，计数器，编程脉冲应用次数存储单元和程序启动电压设置单元。 页缓冲器被配置为当编程为超过包括在单页中的目标程序单元中的参考电压的单元存在时，输出1位通过信号。 计数器配置为对用于确定编程脉冲应用编号的程序脉冲数进行计数。 编程脉冲应用次数存储单元被配置为存储施加的编程脉冲数，直到在第一页的编程操作期间接收到1位通过信号。 程序启动电压设定单元被配置为基于存储的程序脉冲应用程序号来设置第二页的程序启动电压。

公开(公告)号：US20090292860A1

公开(公告)日：2009-11-26

申请号：US12164015

申请日：2008-06-28

申请人： Seong Je PARK

发明人： Seong Je PARK

IPC分类号： G06F12/02

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C2211/5642

摘要： The present invention relates to a method of programming a non-volatile memory device. A method of programming an non-volatile memory device in accordance with an aspect of the present invention includes inputting n page of data, storing a single page of data in each of page buffer units of a plurality of memory cell units, programming a first page of data stored in a page buffer unit of a first memory cell unit, transferring a second page of data, stored in a page buffer unit of a second memory cell unit, to the page buffer unit of the first memory cell unit, and programming the transferred second page of data into the first memory cell unit.

摘要翻译： 本发明涉及一种编程非易失性存储器件的方法。 根据本发明的一个方面的编程非易失性存储器件的方法包括：输入n页数据，在多个存储单元单元的每个页缓冲器单元中存储单页数据，编程第一页 存储在第一存储单元单元的页缓冲器单元中的数据，将存储在第二存储单元单元的页缓冲器单元中的第二数据页传送到第一存储单元单元的页缓冲器单元，并对 将第二页数据传送到第一存储单元单元。

公开(公告)号：US20090040832A1

公开(公告)日：2009-02-12

申请号：US11965999

申请日：2007-12-28

申请人： Seong Je PARK

发明人： Seong Je PARK

IPC分类号： G11C16/34

CPC分类号： G11C16/3404 ,  G11C16/0483

摘要： A soft program method in a non-volatile memory device for performing a soft program step so as to improve threshold voltage distribution of an erased cell is disclosed. The soft program method in a non-volatile memory device includes performing a soft program for increasing threshold voltages of memory cells by a given level, wherein an erase operation is performed about the memory cells, performing a verifying operation for verifying whether or not a cell programmed to a voltage more than a verifying voltage is existed in each of cell strings, and performing repeatedly the soft program until it is verified that whole cell strings have one or more cell programmed to the voltage more than the verifying voltage.

摘要翻译： 公开了一种用于执行软编程步骤以改善已擦除单元的阈值电压分布的非易失性存储器件中的软编程方法。 非易失性存储器件中的软编程方法包括执行用于将存储器单元的阈值电压提高给定电平的软程序，其中对存储器单元执行擦除操作，执行验证操作以验证单元 被编程为在每个单元串中存在大于验证电压的电压，并且重复执行软程序，直到验证整个单元串具有被编程为多于验证电压的电压的一个或多个单元串。