公开(公告)号：US07176718B1

公开(公告)日：2007-02-13

申请号：US11040457

申请日：2005-01-21

Applicant: Michael D Hutton ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  David Lewis ,  Tim Vanderhoek

Inventor： Michael D Hutton ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  David Lewis ,  Tim Vanderhoek

IPC: H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/17728

Abstract: A programmable logic element grouping for use in multiple instances on a programmable logic device includes more than the traditional number of logic elements sharing secondary signal (e.g., clock, clock enable, clear, etc.) selection circuitry. The logic elements in such a grouping are divided into at least two subgroups. Programmable interconnection circuitry is provided for selectively applying signals from outside the grouping and signals fed back from the logic elements in the grouping to primary inputs of the logic elements in the grouping. The programmable interconnection circuitry limits possible application of at least some of these signals to one or the other of the subgroups, and/or provides for possible application of at least some of these signals to a greater percentage of the primary inputs to one of the subgroups than to the other.

Abstract translation: 在可编程逻辑器件上的多个实例中使用的可编程逻辑元件组合包括多于共享次级信号（例如，时钟，时钟使能，清零等）选择电路的传统数量的逻辑元件。 这种分组中的逻辑元素被划分为至少两个子组。 提供了可编程互连电路，用于选择性地将分组外的信号和分组中的逻辑元件反馈的信号分组中的逻辑元件的主要输入。 可编程互连电路将这些信号中的至少一些信号的可能应用限制到子组中的一个或另一个，并且/或提供这些信号中的至少一些信号到其中一个子组的较大百分比的主要输入的可能应用 比对方。

公开(公告)号：US20060017460A1

公开(公告)日：2006-01-26

申请号：US11189549

申请日：2005-07-25

Applicant: David Lewis ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  Andy Lee

Inventor： David Lewis ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  Andy Lee

IPC: H03K19/177

CPC classification number: H03K19/17728 ,  H03K19/1737

Abstract: A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexers with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output. The controls are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.

Abstract translation: 逻辑元件包括存储器元件，多路复用器和控制器。 多路复用器被布置在包括最高级别的多路复用器的级别中，其中连接到存储器元件的输入端和连接到下一级到最高级复用器的输出的输出端和第一级多路复用器，其输入端连接到第二级 多路复用器和至少一个输出。 控制器连接到多路复用器。 在第一操作模式中，所述控制确定所述第一级多路复用器的所述至少一个输出处的第一模式输出，并且在第二操作模式中，所述控制确定多路复用器的选定输出处的多个第二模式输出， 第一级多路复用器。

公开(公告)号：US06747480B1

公开(公告)日：2004-06-08

申请号：US10195209

申请日：2002-07-12

Applicant: Sinan Kaptanoglu ,  Michael D. Hutton ,  James Schleicher

Inventor： Sinan Kaptanoglu ,  Michael D. Hutton ,  James Schleicher

IPC: H03K19177

CPC classification number: H03K19/17748 ,  H03K19/1737 ,  H03K19/17736

Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. The regions of logic may include logic subregions that each have a look-up table. Interconnection resources (e.g., inter-region and intra-region interconnection conductors, signal buffers and drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections between the look-up tables. Programmable bidirectional cascade circuitry that is distinct from the interconnections may be used to make connections directly from the output of one look-up table to another without using the interconnection resources. The programmable cascade circuitry may be programmed so that multiple look-up tables are interconnected to form sequential cascade chains or cascade trees.

Abstract translation: 可编程逻辑集成电路器件具有多个可编程逻辑区域，该多个可编程逻辑区域设置在该区域的多个相交行和列中的该器件上。 逻辑区域可以包括各自具有查找表的逻辑子区域。 在设备上提供互连资源（例如，区域间和区域内互连导体，信号缓冲器和驱动器，可编程连接器等），用于在查找表之间进行可编程互连。 与互连不同的可编程双向级联电路可用于使连接从一个查找表的输出直接连接到另一个查找表，而不使用互连资源。 可编程级联电路可以被编程，使得多个查找表互连以形成顺序级联链或级联树。

公开(公告)号：US06636930B1

公开(公告)日：2003-10-21

申请号：US09519312

申请日：2000-03-06

Applicant: Sinan Kaptanoglu

Inventor： Sinan Kaptanoglu

IPC: G06F1300

CPC classification number: H03K19/17736 ,  H03K19/17796

Abstract: An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16×16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery. A B16×16 tile in the middle level of hierarchy is a sixteen by sixteen array of B1 blocks. The B16×16 tile is a nesting of a B2×2 tile that includes a two by two array of four B1 blocks. The routing resources in the middle level of hierarchy are expressway routing channels M1, M2, and M3 including groups of interconnect conductors. The expressway routing channels M1, M2, and M3 are segmented, and between each of the segments in the expressway routing channels M1, M2, and M3 are disposed extensions that can extend the expressway routing channel M1, M2, or M3 an identical distance along the same direction. The expressway routing channels M1, M2, and M3 run both vertically through every column and horizontally through every row of B2×2 tiles. At the intersections of each of the expressway routing channels M1, M2, and M3 in the horizontal direction with the expressway routing channels M1, M2 and M3 in the vertical direction is an expressway turn (E-turn) disposed at the center of each B2×2 tile. An E-turn is a passive device that includes a matrix of reprogrammable switches. The reprogrammable switches are preferably a pass device controlled by an SRAM bit. The interconnect conductors in the expressway routing channels M1, M2 and M3 that are fed into an E-turn may be coupled to many of the other interconnect conductors in the expressway routing channels M1, M2 and M3 that come into the E-turn by the programmable switches. Further, the interconnect conductors in the expressway routing channels M1, M2 and M3 that are fed into an E-turn continue in the same direction through the E-turn, even though the interconnect conductors are coupled to other interconnect conductors by the reprogrammable switches.

公开(公告)号：US5698992A

公开(公告)日：1997-12-16

申请号：US746554

申请日：1996-11-13

Applicant: Khaled A. El Ayat ,  Gregory W. Bakker ,  Jung-Cheun Lien ,  William C. Plants ,  Sinan Kaptanoglu ,  Runip Gopisetty ,  King W. Chan ,  Marko Chew

Inventor： Khaled A. El Ayat ,  Gregory W. Bakker ,  Jung-Cheun Lien ,  William C. Plants ,  Sinan Kaptanoglu ,  Runip Gopisetty ,  King W. Chan ,  Marko Chew

IPC: H03K19/177 ,  G01R31/28 ,  G01R31/3185 ,  H03K19/173

CPC classification number: G01R31/2884 ,  G01R31/318519 ,  H03K19/17704 ,  H03K19/17728

Abstract: A user-programmable gate array architecture includes an array of logic function modules which may comprise one or more combinatorial and/or sequential logic circuits. An interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels, each including a plurality of interconnect conductors some of which may be segmented, is imposed on the array. Individual ones of the interconnect conductors are connectable to each other and to the inputs and outputs of the logic function modules by user-programmable interconnect elements. A local interconnect architecture comprising local interconnect channels is also imposed on the array. Each local interconnect channel includes a plurality of local interconnect conductors and runs between pairs of adjacent ones of the logic function modules.

Abstract translation: 用户可编程门阵列架构包括可包括一个或多个组合和/或顺序逻辑电路的逻辑功能模块阵列。 包括多个水平和垂直通用互连通道的互连架构，每个通道互连通道包括多个互连导体，其中一些互连导体可能被分段，其被施加在阵列上。 互连导体中的单个导体可通过用户可编程互连元件彼此连接并连接到逻辑功能模块的输入和输出端。 包括本地互连通道的本地互连架构也被施加在阵列上。 每个局部互连通道包括多个局部互连导体并且在相邻的逻辑功能模块对之间运行。

公开(公告)号：US5570041A

公开(公告)日：1996-10-29

申请号：US504051

申请日：1995-06-28

Applicant: Khaled A. El-Avat ,  Sinan Kaptanoglu ,  King W. Chan ,  William C. Plants ,  Jung-Cheun Lien

Inventor： Khaled A. El-Avat ,  Sinan Kaptanoglu ,  King W. Chan ,  William C. Plants ,  Jung-Cheun Lien

IPC: H01L21/82 ,  G01R31/28 ,  G01R31/3185 ,  H03K19/00 ,  H03K19/173 ,  H03K19/177

CPC classification number: G01R31/2884 ,  G01R31/318516 ,  G01R31/318519 ,  H03K19/177 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736

Abstract: A user-programmable gate array architecture includes an array of logic function modules which may comprise one or more combinatorial and/or sequential logic circuits. An interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels, each including a plurality of interconnect conductors some of which may be segmented, is imposed on the array. Individual ones of the interconnect conductors are connectable to each other and to the inputs and outputs of the logic function modules by user-programmable interconnect elements. A local interconnect architecture comprising local interconnect channels is also imposed on the array. Each local interconnect channel includes a plurality of local interconnect conductors and runs between pairs of adjacent ones of the logic function modules.

公开(公告)号：US08543955B1

公开(公告)日：2013-09-24

申请号：US12716999

申请日：2010-03-03

Applicant: Sinan Kaptanoglu ,  David W. Mendel

Inventor： Sinan Kaptanoglu ,  David W. Mendel

IPC: G06F17/50

CPC classification number: H03K19/17748 ,  H03K19/017581 ,  H03K19/177 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/17796

Abstract: A time-multiplexed field programmable gate array (TM-FPGA) includes programmable logic circuitry, programmable interconnect circuitry, and a plurality of context registers. A user's circuit can be mapped to the programmable logic circuitry, the programmable interconnect circuitry, and the plurality of context registers without the user's intervention in mapping the design.

Abstract translation: 时间复用的现场可编程门阵列（TM-FPGA）包括可编程逻辑电路，可编程互连电路和多个上下文寄存器。 用户的电路可以映射到可编程逻辑电路，可编程互连电路和多个上下文寄存器，而无需用户对设计进行映射。

公开(公告)号：US08258811B2

公开(公告)日：2012-09-04

申请号：US13158019

申请日：2011-06-10

Applicant: Samuel W. Beal ,  Sinan Kaptanoglu ,  Jung-Cheun Lien ,  William Shu ,  King W. Chan ,  William C. Plants

Inventor： Samuel W. Beal ,  Sinan Kaptanoglu ,  Jung-Cheun Lien ,  William Shu ,  King W. Chan ,  William C. Plants

IPC: H03K19/177

CPC classification number: H03K19/17768 ,  H03K19/1736 ,  H03K19/17704 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/17796

Abstract: An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.

Abstract translation: 增强的性能现场可编程门阵列集成电路包括现场可编程门阵列和其它功能电路，例如同一集成电路中的掩模可编程门阵列。 电路接口提供现场可编程门阵列，掩模可编程门阵列和集成电路I / O之间的通信。

公开(公告)号：US08225259B1

公开(公告)日：2012-07-17

申请号：US11129796

申请日：2005-05-16

Applicant: David W. Mendel ,  Sinan Kaptanoglu

Inventor： David W. Mendel ,  Sinan Kaptanoglu

IPC: G06F17/50

CPC classification number: H03K19/17748 ,  H03K19/017581 ,  H03K19/177 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/17796

Abstract: A multiple-clock time-multiplexed field programmable gate array (TM-FPGA) includes programmable logic circuitry. A plurality of clock signals within the TM-FPGA couple to the programmable logic circuitry. A user's circuit can be mapped to the programmable logic circuitry without the user's intervention in mapping the circuit to the programmable logic circuitry.

Abstract translation: 多时钟时间复用现场可编程门阵列（TM-FPGA）包括可编程逻辑电路。 TM-FPGA内的多个时钟信号耦合到可编程逻辑电路。 用户的电路可以映射到可编程逻辑电路，而无需用户介入将电路映射到可编程逻辑电路。

公开(公告)号：US08217678B1

公开(公告)日：2012-07-10

申请号：US12834404

申请日：2010-07-12

Applicant: David Lewis ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  Andy L. Lee

Inventor： David Lewis ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  Andy L. Lee

IPC: H03K19/173

CPC classification number: H03K19/177

Abstract: A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexers with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output. The controls are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.

Abstract translation: 逻辑元件包括存储器元件，多路复用器和控制器。 多路复用器被布置在包括最高级别的多路复用器的级别中，其中连接到存储器元件的输入端和连接到下一级到最高级复用器的输出的输出端和第一级多路复用器，其输入端连接到第二级 多路复用器和至少一个输出。 控制器连接到多路复用器。 在第一操作模式中，所述控制确定所述第一级多路复用器的所述至少一个输出处的第一模式输出，并且在第二操作模式中，所述控制确定多路复用器的选定输出处的多个第二模式输出， 第一级多路复用器。