公开(公告)号：US12289114B2

公开(公告)日：2025-04-29

申请号：US18678824

申请日：2024-05-30

Applicant: Texas Instruments Incorporated

Inventor： Bhavesh G. Bhakta ,  Venkateswara Reddy Pothireddy ,  Abhijit Kumar Das

IPC: H03L7/081 ,  H03L7/085

Abstract: An example system includes a controller having a first controller terminal, a second controller terminal, and a third controller terminal and digitally locked loop (DLL) circuitry having a first DLL terminal and a second DLL terminal, the first DLL terminal coupled to the first controller terminal. The system also includes first retimer circuitry having a first retimer terminal, and a second retimer terminal, and a third retimer terminal, the first retimer terminal coupled to the second DLL terminal and the second retimer terminal coupled to the second controller terminal and second retimer circuitry having a fourth retimer terminal, a fifth retimer terminal, and a sixth retimer terminal, the fourth retimer terminal coupled to the second DLL terminal and the fifth retimer terminal coupled to the third controller terminal.

公开(公告)号：US12289084B2

公开(公告)日：2025-04-29

申请号：US17588662

申请日：2022-01-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Masahiro Yoshioka ,  Gabriel Hernandez De La Cruz ,  Lawrence Cotton

IPC: H03F3/45 ,  H03F1/30

Abstract: Examples of amplifier circuitry regulate a transconductance value (Gm) of operational transconductance amplifiers (OTAs) in the amplifier to be approximately the same, which value is based on a supply voltage and a reference voltage applied to a reference OTA and the internal resistance of the reference OTA. The reference OTA generates an output current based on Gm and the reference voltage, which current is compared to current generated by the supply voltage and internal resistance of the reference OTA. A tail current transistor of each of the reference OTA and a main OTA that mirrors the Gm of the reference OTA provide a tail current feedback path by which Gm is regulated. Amplifying circuitry is coupled to the main OTA to receive current signals. Based on the received current signals, amplifying circuitry generates a differential output voltage signal. The gain of the amplifying circuitry is proportional to the supply voltage and remains relatively constant across process temperature variations.

公开(公告)号：US20250133780A1

公开(公告)日：2025-04-24

申请号：US18999567

申请日：2024-12-23

Applicant: Texas Instruments Incorporated

Inventor： Binghua Hu ,  Ye Shao ,  John K Arch

IPC: H10D62/10 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/762 ,  H10D64/00 ,  H10D64/27

Abstract: A semiconductor device has a deep trench in a semiconductor substrate of the semiconductor device, with linear trench segments extending to a trench intersection. Adjacent linear trench segments are connected by connector trench segments that surround a substrate pillar in the trench intersection. Each connector trench segment has a width at least as great as widths of the linear trench segments connected by the connector trench segment. The deep trench includes a trench filler material. The deep trench may have three linear trench segments extending to the trench intersection, connected by three connector trench segments, or may have four linear trench segments extending to the trench intersection, connected by four connector trench segments.

公开(公告)号：US20250130737A1

公开(公告)日：2025-04-24

申请号：US18991960

申请日：2024-12-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan Govindarajan ,  Mihir Mody

IPC: G06F3/06 ,  G06F13/28

Abstract: Various systems and methods are provided. One such system includes first and second inputs of first and second types, respectively; a data controller, including a context mapper coupled to the first and second inputs. The data controller includes a context mapper that provides a processing identifier and a storage identifier to each item of data received from the first and second inputs; and a set of processing components, each coupled to the context mapper, and each associated with a respective processing identifier for processing each item of data having the corresponding processing identifier. The system further includes a memory coupled to the context mapper, the memory having multiple storage locations each associated with a respective storage identifier for storing each item of data having the corresponding storage identifier; and first and second outputs of the first and second types, respectively, coupled to the data controller.

公开(公告)号：US12284154B2

公开(公告)日：2025-04-22

申请号：US18405504

申请日：2024-01-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alper S. Akyurek ,  Ariton E. Xhafa ,  Jianwei Zhou ,  Ramanuja Vedantham

IPC: H04L61/5014 ,  H04L61/5092 ,  H04L61/5007 ,  H04L101/604 ,  H04L101/659 ,  H04L101/668

Abstract: A network includes at least two nodes that employ a routing protocol to communicate across a network. One of the nodes is a parent node and another of the nodes is a child node of the parent node. An address generator assigns a unique network address to the child node by appending an address value of a number of bits to a parent address of the parent node to create the unique network address for the child node.

公开(公告)号：US12283259B2

公开(公告)日：2025-04-22

申请号：US17035250

申请日：2020-09-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajesh Narasimha ,  Aziz Umit Batur

IPC: G09G5/377 ,  G06T5/50 ,  G06T5/92 ,  G06T5/94 ,  G06V10/60 ,  H04N23/741 ,  H04N23/743 ,  H04N25/589

Abstract: A method of generating a high dynamic range (HDR) image is provided that includes capturing a long exposure image and a short exposure image of a scene, computing a merging weight for each pixel location of the long exposure image based on a pixel value of the pixel location and a saturation threshold, and computing a pixel value for each pixel location of the HDR image as a weighted sum of corresponding pixel values in the long exposure image and the short exposure image, wherein a weight applied to a pixel value of the pixel location of the short exposure image and a weight applied to a pixel value of the pixel location in the pixel long exposure image are determined based on the merging weight computed for the pixel location and responsive to motion in a scene of the long exposure image and the short exposure image.

公开(公告)号：US12282081B2

公开(公告)日：2025-04-22

申请号：US18159221

申请日：2023-01-25

Applicant: Texas Instruments Incorporated

Inventor： Harish Kumar ,  Srinivasan Venkataraman

IPC: G01R33/00 ,  G01R33/07 ,  G01R35/00

Abstract: A method includes generating a reference voltage by periodically switching direction of current flow in a diagnostic sensor, where the reference voltage is a non-sinusoidal differential voltage of which an amplitude alternates between minimum and maximum values, and where the reference voltage includes a diagnostic sensor output voltage component responsive to an external magnetic field and a diagnostic sensor offset voltage component responsive to a mismatch of the diagnostic sensor. The method also includes amplifying the reference voltage to produce an amplified reference voltage, where the amplified reference voltage is a differential voltage having an amplifier offset voltage component. Additionally, the method includes demodulating the amplified reference voltage by filtering the diagnostic sensor offset voltage component and the amplifier offset voltage component to produce a demodulated voltage. Also, the method includes digitizing the demodulated voltage to produce a digitized voltage.

公开(公告)号：US12278205B2

公开(公告)日：2025-04-15

申请号：US16778250

申请日：2020-01-31

Applicant: Texas Instruments Incorporated

Inventor： Jaimal Mallory Williamson ,  Guangxu Li

IPC: H01L23/48 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498

Abstract: A described example includes a package substrate having an array of die pads arranged in rows and columns on a die mount surface, and having an opposing board side surface; a solder mask layer overlying the die mount surface; a first plurality of solder mask defined openings in the solder mask layer at die pad locations, the solder mask defined openings exposing portions of a surface of corresponding die pads, the surface facing away from the package substrate; and at least one non-solder mask defined opening in the solder mask layer at a die pad location, exposing the entire surface of the die pad and sidewalls of the die pad at the non-solder mask defined opening.

公开(公告)号：US12276761B2

公开(公告)日：2025-04-15

申请号：US17077315

申请日：2020-10-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Subhash Chandra Venkata Sadhu ,  Bharath Patil ,  Jaiganesh Balakrishnan

IPC: G01S7/48 ,  G01S7/484 ,  G01S7/486 ,  G01S7/4865 ,  G01S7/4911 ,  G01S17/10 ,  G01S17/34 ,  G01S17/89 ,  G01S17/894

Abstract: A three dimensional time of flight (TOF) camera includes a transmitter and a receiver. The transmitter is configured to generate an electrical transmit signal at a plurality of frequencies over an integration time period and generate a transmit optical waveform corresponding with the electrical transmit signal. The receiver is configured to receive a reflected optical waveform that is the transmit optical waveform reflected off of an object, integrate the reflected optical waveform over the integration time period, and determine a distance to the target object based on a TOF of the optical waveform. The integration time period includes exposure time periods. A length of each of the exposure time periods corresponds to one of the frequencies. The TOF is determined based on a correlation of the electrical transmit signal and the return optical waveform utilizing a correlation function with respect to the integration time period.

公开(公告)号：US20250120169A1

公开(公告)日：2025-04-10

申请号：US18982600

申请日：2024-12-16

Applicant: Texas Instruments Incorporated

Inventor： Robert Martin Higgins ,  Xiaoju Wu ,  Li Wang ,  Venugopal Balakrishna Menon

IPC: H01L27/06 ,  H01L21/762

Abstract: A method of manufacturing an electronic device includes forming a shallow trench isolation (STI) structure on or in a semiconductor surface layer and forming a mask on the semiconductor surface layer, where the mask exposes a surface of a dielectric material of the STI structure and a prospective local oxidation of silicon (LOCOS) portion of a surface of the semiconductor surface layer. The method also includes performing an oxidation process using the mask to oxidize silicon in an indent in the dielectric material of the STI structure and to grow an oxide material on the exposed LOCOS portion of the surface of the semiconductor surface layer.