公开(公告)号：US5885865A

公开(公告)日：1999-03-23

申请号：US851689

申请日：1997-05-06

申请人： Mong-Song Liang ,  Julie Huang ,  Tse-Liang Ying ,  Chen-Jong Wang

发明人： Mong-Song Liang ,  Julie Huang ,  Tse-Liang Ying ,  Chen-Jong Wang

IPC分类号： E04G23/02 ,  E04B1/64 ,  H01L21/8242

CPC分类号： E04B1/648

摘要： The present invention discloses a method for making low-topography buried capacitor including the steps of first depositing oxide layers, and then forming a small pre-contact hole by a dry etch method and a large contact hole by a wet etch method while using silicon nitride caps and sidewall spacers previously deposited on the word lines and on the bit lines as etch stop layers. A buried capacitor that has significantly improved topography can be fabricated in a semiconductor device.

摘要翻译： 本发明公开了一种制备低地埋式电容器的方法，包括以下步骤：首先沉积氧化物层，然后通过干蚀刻法和大型接触孔通过湿法蚀刻法形成小预接触孔，同时使用氮化硅 预先沉积在字线和位线上的帽和侧壁间隔作为蚀刻停止层。 可以在半导体器件中制造具有显着改善的形貌的埋电容器。

公开(公告)号：US5753547A

公开(公告)日：1998-05-19

申请号：US789238

申请日：1997-01-28

申请人： Tse-Liang Ying

发明人： Tse-Liang Ying

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： The present invention provides a method of manufacturing a stacked cylindrical capacitor having a smooth top cylindrical surface and uniform height. A first insulating layer 20 is formed over the substrate 10. A barrier layer 22 having an opening 23 is formed over a first insulating layer 20 on a substrate. A second insulating layer 24 composed of silicon oxide is formed on the barrier layer 22. The second insulating layer 24 and the first insulating layer 20 are patterned forming a first cylindrical opening 26 exposing the active region of the substrate 10 and forming a second cylindrical opening 30 in the second insulating layer 24 that exposes portions of the barrier layer 22. A conformal polysilicon layer 34 is formed over the resultant surface and the walls of the cylindrical openings 26 30. A planarizing layer 36 is formed over the resulting surface and then etched back forming a planarizing plug 36A that partially fills the second cylindrical opening 30A. A third insulation layer 40 is formed over resultant surface. The third insulating layer 40 and the polysilicon layer 34 are isotropically etched back forming a cylindrical bottom electrode 44 with a smooth top surface 44A. The smooth top electrode surface 44A increases the breakdown voltage to the capacitor.

摘要翻译： 本发明提供一种制造具有平滑顶部圆柱形表面和均匀高度的层叠圆柱形电容器的方法。 第一绝缘层20形成在衬底10上。具有开口23的阻挡层22形成在衬底上的第一绝缘层20上。 在阻挡层22上形成由氧化硅构成的第二绝缘层24.对第二绝缘层24和第一绝缘层20进行图案化，形成露出基板10的有源区的第一圆柱形开口26，并形成第二圆柱形开口 在第二绝缘层24中暴露出阻挡层22的一部分。在合成的表面和圆柱形开口26,30的壁上形成共形多晶硅层34.平坦化层36形成在所得表面上，然后蚀刻 后部形成部分填充第二圆柱形开口30A的平坦化塞子36A。 在合成表面上形成第三绝缘层40。 第三绝缘层40和多晶硅层34被各向同性地回蚀，形成具有光滑顶表面44A的圆柱形底电极44。 光滑的顶部电极表面44A增加了对电容器的击穿电压。

公开(公告)号：US07541205B2

公开(公告)日：2009-06-02

申请号：US11684540

申请日：2007-03-09

申请人： Tse-Liang Ying ,  Shi-Ming Chen

发明人： Tse-Liang Ying ,  Shi-Ming Chen

IPC分类号： H01L21/00

CPC分类号： H01L33/42 ,  Y10S438/956

摘要： A method for forming a transparent electrode on a visible light-emitting diode is described. A visible light-emitting diode element is provided, and the visible light-emitting diode element has a substrate, an epitaxial structure and a metal electrode. The metal electrode and the epitaxial structure are located on the same side of the substrate, or located respectively on the different sides of the substrate. An ohmic metal layer is formed on a surface of the epitaxial structure. The ohmic metal layer is annealed. The ohmic metal layer is removed to expose the surface of the epitaxial structure. A transparent electrode layer is formed on the exposed surface. A metal pad is formed on the transparent electrode layer.

摘要翻译： 描述了在可见光发光二极管上形成透明电极的方法。 提供了可见光发光二极管元件，可见光发光二极管元件具有基板，外延结构和金属电极。 金属电极和外延结构位于基板的同一侧，或分别位于基板的不同侧。 在外延结构的表面上形成欧姆金属层。 欧姆金属层退火。 去除欧姆金属层以露出外延结构的表面。 在露出的表面上形成透明电极层。 在透明电极层上形成金属焊盘。

公开(公告)号：US20060035398A1

公开(公告)日：2006-02-16

申请号：US10938309

申请日：2004-09-09

申请人： Tse-Liang Ying ,  Shi-Ming Chen

发明人： Tse-Liang Ying ,  Shi-Ming Chen

IPC分类号： H01L21/00

CPC分类号： H01L33/42 ,  Y10S438/956

摘要： A method for forming a transparent electrode on a visible light-emitting diode is described. A visible light-emitting diode element is provided, and the visible light-emitting diode element has a substrate, an epitaxial structure and a metal electrode. The metal electrode and the epitaxial structure are located on the same side of the substrate, or located respectively on the different sides of the substrate. An ohmic metal layer is formed on a surface of the epitaxial structure. The ohmic metal layer is annealed. The ohmic metal layer is removed to expose the surface of the epitaxial structure. A transparent electrode layer is formed on the exposed surface. A metal pad is formed on the transparent electrode layer.

公开(公告)号：US06307213B1

公开(公告)日：2001-10-23

申请号：US09617427

申请日：2000-07-14

申请人： Kuo Ching Huang ,  Tse-Liang Ying ,  Cheng Yeh Shih ,  Yu Hua Lee ,  Cheng-Ming Wu

发明人： Kuo Ching Huang ,  Tse-Liang Ying ,  Cheng Yeh Shih ,  Yu Hua Lee ,  Cheng-Ming Wu

IPC分类号： H01L2904

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention relates to a novel fuse structure and method for deleting redundant circuit elements on integrated circuits. This fuse structure is useful for increasing the repair yield on RAM chips by deleting defective rows of memory cells. The method involves forming a fuse area in a patterned electrically conducting layer also used to form interconnections. A relatively thin (0.4 um) insulating layer is deposited having a uniform thickness across the substrate. The next level of patterned interconnections is formed with a portion of the layer aligned over the fuse area to serve as an etch-stop layer. For example, the conducting layers can be the first and second poly-silicon layers on a RAM chip. The remaining multilevel of interconnections is then formed having a number of relatively thick interlevel dielectric (ILD) layers interposed which can have an accumulative large variation in thickness across the substrate. Fuse windows (openings) are then selectively etched in the ILD layers to the etch-stop layer and the etch-stop layer is selectively etched in the fuse window to the insulating layer over the fuse area. This process allows fuse structures to be built without overetching that can cause fuse damage. The uniform thick insulating layer allows repeatable and reliable laser abrading (evaporation) to open the desired fuses.

摘要翻译： 本发明涉及一种用于删除集成电路上的冗余电路元件的新型熔丝结构和方法。 该熔丝结构可用于通过删除存储单元的有缺陷的行来增加RAM芯片的修复产量。 该方法包括在也用于形成互连的图案化导电层中形成熔丝区域。 沉积相对薄的（0.4μm）绝缘层，其跨越衬底具有均匀的厚度。 下一级图案互连形成，其中一部分层在保险丝区域上对齐以用作蚀刻停止层。 例如，导电层可以是RAM芯片上的第一和第二多晶硅层。 然后形成剩余的多层互连件，其具有插入的多个相对较厚的层间电介质层（ILD）层，其可跨越衬底具有累积的厚度变化。 然后在ILD层中选择性地将保险丝窗（开口）蚀刻到蚀刻停止层，并且将蚀刻停止层选择性地在保险丝窗口中蚀刻到保险丝区域上的绝缘层。 该过程允许熔断器结构被建立，而不会导致熔断器损坏。 均匀的厚绝缘层允许可重复且可靠的激光研磨（蒸发）来打开所需的保险丝。

公开(公告)号：US06306767B1

公开(公告)日：2001-10-23

申请号：US09584111

申请日：2000-05-31

申请人： Kuo-Chyuan Tzeng ,  Tse-Liang Ying ,  Wen-Chuan Chiang ,  Ming-Hsiang Chiang

发明人： Kuo-Chyuan Tzeng ,  Tse-Liang Ying ,  Wen-Chuan Chiang ,  Ming-Hsiang Chiang

IPC分类号： H01L21302

CPC分类号： H01L27/10888 ,  H01L21/32139 ,  H01L27/10811

摘要： Within a method for forming a patterned layer there is first provided a topographic substrate. There is then formed conformally over the topographic substrate a blanket target layer formed of a target material, where the blanket target layer has a lower substantially horizontal portion, an upper substantially horizontal portion and an intermediate portion therebetween. There is then formed upon the lower substantially horizontal portion of the blanket target layer a first masking layer formed of a first masking material and formed upon the upper substantially horizontal portion of the blanket target layer a second masking layer formed of a second masking material. There is then etched, while employing an etch method having an enhanced sequential selectivity for the first masking material and the target material with respect to the second masking material, the first masking layer and the lower substantially horizontal portion of the blanket target layer to form a patterned target layer which leaves exposed a portion of the substrate beneath the lower horizontal portion of the blanket target layer while leaving unetched the upper substantially horizontal portion of the blanket target layer. The method is particularly useful for forming patterned capacitor plate layers.

摘要翻译： 在形成图案层的方法中，首先提供地形衬底。 然后，在地形基底上形成由目标材料形成的覆盖目标层，其中覆盖层目标层具有下部基本水平的部分，上部基本水平的部分和在其间的中间部分。 然后，在覆盖目标层的下部基本水平的部分上形成由第一掩模材料形成并形成在覆盖目标层的上部基本水平的部分上的第一掩蔽层，第二掩蔽层由第二掩蔽材料形成。 然后蚀刻，同时采用对于第一掩蔽材料和靶材料相对于第二掩蔽材料具有增强的顺序选择性的蚀刻方法，覆盖目标层的第一掩蔽层和下部基本水平的部分，以形成 图案化目标层，其在衬底目标层的下部水平部分的下方露出衬底的一部分，同时保留未覆盖的覆盖目标层的上部基本水平的部分。 该方法对于形成图案化电容器板层特别有用。

公开(公告)号：US06174802B1

公开(公告)日：2001-01-16

申请号：US09342042

申请日：1999-06-28

申请人： Kuo-Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang ,  Min-Hsiung Chiang

发明人： Kuo-Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang ,  Min-Hsiung Chiang

IPC分类号： H01L214763

CPC分类号： H01L21/76897

摘要： A method for forming a self aligned contact without key holes using a two step contact deposition. The process begins by providing a semiconductor structure having conductive structures (such as bit lines) thereover with sidewalls and having a contact area adjacent to the conductive structures. The conductive structures comprise at least one conductive layer with a hard mask thereover. A spacer layer is formed over the hard mask and the substrate structure and anisotropically etched to form sidewall spacers on the sidewalls of the conductive structure. A second dielectric (IPO) layer is formed over the sidewall spacers, the hard mask, and the substrate structure, whereby the second dielectric layer has a keyhole. A contact opening is formed in the second dielectric layer over the contact area. A first contact layer having poor step coverage is formed in the contact openings and over the second dielectric layer, thereby plugging the keyhole without filling it. A second contact layer is formed over the first contact layer.

摘要翻译： 使用两步接触沉积形成无键孔的自对准接触的方法。 该过程开始于提供具有导电结构（例如位线）的半导体结构，其具有侧壁并且具有与导电结构相邻的接触区域。 导电结构包括至少一个具有硬掩模的导电层。 在硬掩模和衬底结构之上形成间隔层，并且各向异性蚀刻以在导电结构的侧壁上形成侧壁间隔物。 在侧壁间隔物，硬掩模和基板结构上方形成第二电介质层（IPO），由此第二介电层具有锁孔。 在接触区域上的第二电介质层中形成接触开口。 在接触开口和第二电介质层上形成具有差的台阶覆盖率的第一接触层，从而在不填充锁孔的情况下封闭钥匙孔。 在第一接触层上形成第二接触层。

公开(公告)号：US6121073A

公开(公告)日：2000-09-19

申请号：US24479

申请日：1998-02-17

申请人： Kuo Ching Huang ,  Tse-Liang Ying ,  Cheng Yeh Shih ,  Yu Hua Lee ,  Cheng-Ming Wu

发明人： Kuo Ching Huang ,  Tse-Liang Ying ,  Cheng Yeh Shih ,  Yu Hua Lee ,  Cheng-Ming Wu

IPC分类号： H01L23/525 ,  H01L21/82 ,  H01L27/10

CPC分类号： H01L23/5258 ,  H01L2924/0002

摘要： This invention relates to a novel fuse structure and method for deleting redundant circuit elements on integrated circuits. This fuse structure is useful for increasing the repair yield on RAM chips by deleting defective rows of memory cells. The method involves forming a fuse area in a patterned electrically conducting layer also used to form interconnections. A relatively thin (0.4 um) insulating layer is deposited having a uniform thickness across the substrate. The next level of patterned interconnections is formed with a portion of the layer aligned over the fuse area to serve as an etch-stop layer. For example, the conducting layers can be the first and second polysilicon layers on a RAM chip. The remaining multilevel of interconnections is then formed having a number of relatively thick interlevel dielectric (ILD) layers interposed which can have an accumulative large variation in thickness across the substrate. Fuse windows (openings) are then selectively etched in the ILD layers to the etch-stop layer and the etch-stop layer is selectively etched in the fuse window to the insulating layer over the fuse area. This process allows fuse structures to be built without overetching that can cause fuse damage. The uniform thick insulating layer allows repeatable and reliable laser abrading (evaporation) to open the desired fuses.

摘要翻译： 本发明涉及一种用于删除集成电路上的冗余电路元件的新型熔丝结构和方法。 该熔丝结构可用于通过删除存储单元的有缺陷的行来增加RAM芯片的修复产量。 该方法包括在也用于形成互连的图案化导电层中形成熔丝区域。 沉积相对薄的（0.4μm）绝缘层，其跨越衬底具有均匀的厚度。 下一级图案互连形成，其中一部分层在保险丝区域上对齐以用作蚀刻停止层。 例如，导电层可以是RAM芯片上的第一和第二多晶硅层。 然后形成剩余的多层互连件，其具有插入的多个相对较厚的层间电介质层（ILD）层，其可跨越衬底具有累积的厚度变化。 然后在ILD层中选择性地将保险丝窗（开口）蚀刻到蚀刻停止层，并且将蚀刻停止层选择性地在保险丝窗口中蚀刻到保险丝区域上的绝缘层。 该过程允许熔断器结构被建立，而不会导致熔断器损坏。 均匀的厚绝缘层允许可重复且可靠的激光研磨（蒸发）来打开所需的保险丝。

公开(公告)号：US6093619A

公开(公告)日：2000-07-25

申请号：US99809

申请日：1998-06-18

申请人： Kuo Ching Huang ,  Tse-Liang Ying ,  Chia-Shiung Tsai

发明人： Kuo Ching Huang ,  Tse-Liang Ying ,  Chia-Shiung Tsai

IPC分类号： H01L21/762 ,  H01L21/768 ,  H01L21/76

CPC分类号： H01L21/76224 ,  H01L21/76895

摘要： A new method of forming a buried contact junction in a process involving shallow trench isolation is described. A first silicon oxide layer is deposited over a pad oxide layer on the surface of a semiconductor substrate. An opening is etched in the first silicon nitride and pad oxide layers where they are not covered by a mask. The substrate underlying the opening is etched into to form a shallow trench. An oxide material is deposited over the surface of the first silicon nitride layer and within the shallow trench and planarized to the surface of the first silicon nitride layer wherein the oxide material forms a STI region. The first silicon nitride layer is removed whereby the STI protrudes above the pad oxide layer. The pad oxide layer is removed whereby the corners of the STI above the substrate are also removed. A second silicon nitride layer is deposited overlying a sacrificial oxide layer and etched away to leave silicon nitride spacers filling in and rounding the corners of the STI. The sacrificial oxide layer is removed. A gate electrode and source/drain regions are formed in and on the substrate wherein a source/drain is adjacent to the STI. The gate electrode and STI are covered with an insulating layer. An opening is etched through the insulating layer to the source/drain region wherein the silicon nitride spacer at the corner of the STI prevents etching of the STI. The opening is filled with a conducting layer to complete formation of a contact.

摘要翻译： 描述了在涉及浅沟槽隔离的过程中形成掩埋接触结的新方法。 在半导体衬底的表面上的衬垫氧化物层上沉积第一氧化硅层。 在第一氮化硅和衬垫氧化物层中蚀刻开口，其中它们不被掩模覆盖。 蚀刻开口下方的基板以形成浅沟槽。 氧化物材料沉积在第一氮化硅层的表面上并在浅沟槽内，并且平坦化到第一氮化硅层的表面，其中氧化物材料形成STI区域。 去除第一氮化硅层，由此STI突出到衬垫氧化物层的上方。 移除衬垫氧化物层，从而也去除衬底上方的STI的拐角。 将第二氮化硅层沉积在牺牲氧化物层上并被蚀刻掉以留下氮化硅间隔物填充到STI的角部并使其四周。 去除牺牲氧化物层。 栅极电极和源极/漏极区域形成在衬底中和衬底上，其中源极/漏极与STI相邻。 栅电极和STI被绝缘层覆盖。 通过绝缘层蚀刻开口到源极/漏极区域，其中STI的拐角处的氮化硅间隔物防止STI的蚀刻。 开口填充有导电层以完成接触的形成。