-
1.发明授权Self-aligned etching method for forming high areal density patterned microelectronic structures 有权用于形成高密度图案的微电子结构的自对准蚀刻方法公开(公告)号：US06306767B1
公开(公告)日：2001-10-23
申请号：US09584111
申请日：2000-05-31
IPC分类号： H01L21302
CPC分类号： H01L27/10888 , H01L21/32139 , H01L27/10811
摘要： Within a method for forming a patterned layer there is first provided a topographic substrate. There is then formed conformally over the topographic substrate a blanket target layer formed of a target material, where the blanket target layer has a lower substantially horizontal portion, an upper substantially horizontal portion and an intermediate portion therebetween. There is then formed upon the lower substantially horizontal portion of the blanket target layer a first masking layer formed of a first masking material and formed upon the upper substantially horizontal portion of the blanket target layer a second masking layer formed of a second masking material. There is then etched, while employing an etch method having an enhanced sequential selectivity for the first masking material and the target material with respect to the second masking material, the first masking layer and the lower substantially horizontal portion of the blanket target layer to form a patterned target layer which leaves exposed a portion of the substrate beneath the lower horizontal portion of the blanket target layer while leaving unetched the upper substantially horizontal portion of the blanket target layer. The method is particularly useful for forming patterned capacitor plate layers.
摘要翻译： 在形成图案层的方法中，首先提供地形衬底。 然后，在地形基底上形成由目标材料形成的覆盖目标层，其中覆盖层目标层具有下部基本水平的部分，上部基本水平的部分和在其间的中间部分。 然后，在覆盖目标层的下部基本水平的部分上形成由第一掩模材料形成并形成在覆盖目标层的上部基本水平的部分上的第一掩蔽层，第二掩蔽层由第二掩蔽材料形成。 然后蚀刻，同时采用对于第一掩蔽材料和靶材料相对于第二掩蔽材料具有增强的顺序选择性的蚀刻方法，覆盖目标层的第一掩蔽层和下部基本水平的部分，以形成 图案化目标层，其在衬底目标层的下部水平部分的下方露出衬底的一部分，同时保留未覆盖的覆盖目标层的上部基本水平的部分。 该方法对于形成图案化电容器板层特别有用。
-
公开(公告)号：US06794254B1
公开(公告)日：2004-09-21
申请号：US10438646
申请日：2003-05-15
IPC分类号： H01L21336
CPC分类号： H01L27/1087 , H01L27/10894
摘要： A new method to form DRAM cells in an integrated circuit device is achieved. The method comprises providing a substrate. A plurality of STI regions is formed in the substrate. The STI regions comprise trenches in the substrate. The trenches are filled with a first dielectric layer. All of the first dielectric layer is etched away from a first group of the STI regions to form open trenches while leaving the first dielectric layer in a second group of the STI regions. A second dielectric layer is formed overlying the substrate and lining the open trenches. A conductive layer is deposited overlying the second dielectric layer and completely filling the open trenches. The conductive layer is patterned to define DRAM transistor gates and to define DRAM capacitor top plates. Thereafter, ions are implanted into the substrate to form source and drain regions for the transistors.
摘要翻译： 实现了在集成电路器件中形成DRAM单元的新方法。 该方法包括提供基底。 在衬底中形成多个STI区。 STI区域包括衬底中的沟槽。 沟槽填充有第一介电层。 所有第一电介质层被蚀刻离开第一组STI区域以形成开放沟槽，同时将第一介电层留在STI区域的第二组中。 第二电介质层形成在衬底上并衬衬开放的沟槽。 沉积覆盖第二介电层并完全填充开放沟槽的导电层。 图案化导电层以限定DRAM晶体管栅极并且限定DRAM电容器顶板。 此后，将离子注入衬底以形成用于晶体管的源极和漏极区域。
-
公开(公告)号：US20050017285A1
公开(公告)日：2005-01-27
申请号：US10920492
申请日：2004-08-18
IPC分类号： H01L21/336 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/1087 , H01L27/10894
摘要： A new method to form DRAM cells in an integrated circuit device is achieved. The method comprises providing a substrate. A plurality of STI regions is formed in the substrate. The STI regions comprise trenches in the substrate. The trenches are filled with a first dielectric layer. All of the first dielectric layer is etched away from a first group of the STI regions to form open trenches while leaving the first dielectric layer in a second group of the STI regions. A second dielectric layer is formed overlying the substrate and lining the open trenches. A conductive layer is deposited overlying the second dielectric layer and completely filling the open trenches. The conductive layer is patterned to define DRAM transistor gates and to define DRAM capacitor top plates. Thereafter, ions are implanted into the substrate to form source and drain regions for the transistors.
摘要翻译： 实现了在集成电路器件中形成DRAM单元的新方法。 该方法包括提供基底。 在衬底中形成多个STI区。 STI区域包括衬底中的沟槽。 沟槽填充有第一介电层。 所有第一电介质层被蚀刻离开第一组STI区域以形成开放沟槽，同时将第一介电层留在STI区域的第二组中。 第二电介质层形成在衬底上并衬衬开放的沟槽。 沉积覆盖第二介电层并完全填充开放沟槽的导电层。 图案化导电层以限定DRAM晶体管栅极并且限定DRAM电容器顶板。 此后，将离子注入衬底以形成用于晶体管的源极和漏极区域。
-
公开(公告)号：US07091543B2
公开(公告)日：2006-08-15
申请号：US10920492
申请日：2004-08-18
IPC分类号： H01L27/108
CPC分类号： H01L27/1087 , H01L27/10894
摘要： A new method to form DRAM cells in an integrated circuit device is achieved. The method comprises providing a substrate. A plurality of STI regions is formed in the substrate. The STI regions comprise trenches in the substrate. The trenches are filled with a first dielectric layer. All of the first dielectric layer is etched away from a first group of the STI regions to form open trenches while leaving the first dielectric layer in a second group of the STI regions. A second dielectric layer is formed overlying the substrate and lining the open trenches. A conductive layer is deposited overlying the second dielectric layer and completely filling the open trenches. The conductive layer is patterned to define DRAM transistor gates and to define DRAM capacitor top plates. Thereafter, ions are implanted into the substrate to form source and drain regions for the transistors.
摘要翻译： 实现了在集成电路器件中形成DRAM单元的新方法。 该方法包括提供基底。 在衬底中形成多个STI区。 STI区域包括衬底中的沟槽。 沟槽填充有第一介电层。 所有第一电介质层被蚀刻离开第一组STI区域以形成开放沟槽，同时将第一介电层留在STI区域的第二组中。 第二电介质层形成在衬底上并衬衬开放的沟槽。 沉积覆盖第二介电层并完全填充开放沟槽的导电层。 图案化导电层以限定DRAM晶体管栅极并且限定DRAM电容器顶板。 此后，将离子注入衬底以形成用于晶体管的源极和漏极区域。
-
5.发明申请Semiconductor Devices with Orientation-Free Decoupling Capacitors and Methods of Manufacture Thereof 有权具有无取向去耦电容器的半导体器件及其制造方法公开(公告)号：US20130020678A1
公开(公告)日：2013-01-24
申请号：US13188343
申请日：2011-07-21
申请人： Kuo-Chi Tu , Kuo-Chyuan Tzeng , Wen-Chuan Chiang , Chen-Jong Wang
发明人： Kuo-Chi Tu , Kuo-Chyuan Tzeng , Wen-Chuan Chiang , Chen-Jong Wang
CPC分类号： H01L27/0207 , H01L28/40
摘要： Semiconductor devices with orientation-free decoupling capacitors and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes at least one integrated circuit and at least one decoupling capacitor. The at least one decoupling capacitor is oriented in a different direction than the at least one integrated circuit is oriented.
摘要翻译： 公开了具有无取向去耦电容器的半导体器件及其制造方法。 在一个实施例中，半导体器件包括至少一个集成电路和至少一个去耦电容器。 至少一个去耦电容器被定向在与至少一个集成电路取向的方向不同的方向上。
-
6.发明授权Method of forming a composite spacer to eliminate polysilicon stringers between elements in a pseudo SRAM cell 有权形成复合间隔物以消除伪SRAM单元中的元件之间的多晶硅桁条的方法公开(公告)号：US06638813B1
公开(公告)日：2003-10-28
申请号：US10059825
申请日：2002-01-29
申请人： Kuo-Chyuan Tzeng , Chen-Jong Wang , Chung-Wei Chang , Wen-Chuan Chiang , Wen-Cheng Chen , Kuo-Ching Huang
发明人： Kuo-Chyuan Tzeng , Chen-Jong Wang , Chung-Wei Chang , Wen-Chuan Chiang , Wen-Cheng Chen , Kuo-Ching Huang
IPC分类号： H01L218242
CPC分类号： H01L28/60 , H01L21/31111 , H01L21/31116 , H01L21/32137 , H01L21/76232 , H01L27/11
摘要： A process for forming a composite insulator spacer on the sides of a buried stack capacitor structure, wherein the buried stack capacitor structure is located overlying a portion of an insulator filled, shallow trench isolation (STI) region, has been developed. A thin silicon nitride spacer is first formed on the sides of the completed buried stack capacitor structure, followed by deposition of a silicon oxide layer. An anisotropic dry etch procedure is next employed removing a top portion of the silicon oxide layer, and resulting in a partially defined silicon oxide spacer. A critical wet etch procedure is next used to remove the bottom portion of the silicon oxide layer, defining the final silicon oxide spacer of the composite insulator spacer, now comprised of a silicon oxide spacer on an underlying silicon nitride spacer. The wet etch procedure allows a gradual slope to be created at the composite insulator spacer—STI region interface, reducing the risk of leaving, or forming polysilicon residuals or stringers on the underlying surface, which can occur during definition of a MOSFET gate structure. The elimination of the polysilicon stringers reduces the risk of leakage between SRAM cell elements, such as buried stack capacitor structures, and MOSFET devices.
摘要翻译： 已经开发了一种用于在掩埋叠层电容器结构的侧面上形成复合绝缘体间隔物的方法，其中埋层叠层电容器结构位于绝缘体填充的浅沟槽隔离（STI）区域的一部分上方。 首先在完成的掩埋堆叠电容器结构的侧面上形成薄的氮化硅间隔物，然后沉积氧化硅层。 接下来，使用各向异性干蚀刻工艺去除氧化硅层的顶部，并产生部分限定的氧化硅间隔物。 接下来使用关键的湿法蚀刻工艺来去除氧化硅层的底部，限定复合绝缘垫片的最终氧化硅隔离物，现在由下面的氮化硅间隔物上的氧化硅间隔物构成。 湿蚀刻工艺允许在复合绝缘体间隔件-ST区域界面处产生逐渐的斜率，从而降低在MOSFET栅极结构的定义期间可能发生的在下表面上的离开风险或形成多晶硅残余物或桁条。 多晶硅桁架的消除降低了诸如掩埋堆叠电容器结构的SRAM单元元件和MOSFET器件之间的泄漏的风险。
-
7.发明授权Semiconductor devices with orientation-free decoupling capacitors and methods of manufacture thereof 有权具有无取向去耦电容器的半导体器件及其制造方法公开(公告)号：US08659121B2
公开(公告)日：2014-02-25
申请号：US13188343
申请日：2011-07-21
申请人： Kuo-Chi Tu , Kuo-Chyuan Tzeng , Wen-Chuan Chiang , Chen-Jong Wang
发明人： Kuo-Chi Tu , Kuo-Chyuan Tzeng , Wen-Chuan Chiang , Chen-Jong Wang
IPC分类号： H01L23/62
CPC分类号： H01L27/0207 , H01L28/40
摘要： Semiconductor devices with orientation-free decoupling capacitors and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes at least one integrated circuit and at least one decoupling capacitor. The at least one decoupling capacitor is oriented in a different direction than the at least one integrated circuit is oriented.
摘要翻译： 公开了具有无取向去耦电容器的半导体器件及其制造方法。 在一个实施例中，半导体器件包括至少一个集成电路和至少一个去耦电容器。 至少一个去耦电容器被定向在与至少一个集成电路取向的方向不同的方向上。
-
8.发明授权Method to define poly dog-bone for word line strapping contact at stitch area in embedded DRAM process 有权在嵌入式DRAM工艺中，针脚区域的字线绑扎接触定义多边形骨的方法公开(公告)号：US06376294B1
公开(公告)日：2002-04-23
申请号：US09755686
申请日：2001-01-08
IPC分类号： H01L218238
CPC分类号： H01L27/10891 , H01L21/823842 , H01L27/10894
摘要： A method for fabricating a dog-bone in a DRAM device, comprising the following steps. A semiconductor structure having an upper silicon layer with STIs formed therein is provided. The semiconductor structure has a LOGIC region and a DRAM region with a stitch region therebetween. A polysilicon layer is formed over the semiconductor structure. A dopant is selectively implanted in the polysilicon region within the DRAM region, and the portion of the stitch region within the DRAM region, to form a doped poly segment, and an undoped poly segment within the LOGIC region, and the portion of the stitch region within the LOGIC region. A hard mask is formed over the doped poly segment and the undoped poly segment and patterned to form at least one patterned first hard mask portion only over the word line doped poly segment within the DRAM region. At least one second mask layer portion is formed over the undoped poly segment within the LOGIC region and at least one third mask layer portion is formed over the doped poly segment in the portion of the stitch region within the DRAM region. The doped poly segment and undoped poly segment are etched to form: undoped poly periphery logic gate portions within the LOGIC region; doped poly dog-bone within the portion of the stitch region within the DRAM region; and doped poly word lines within the DRAM region. The second and third mask layer portions are stripped to expose the undoped poly periphery logic gate portions and the doped poly dog-bone.
摘要翻译： 一种用于在DRAM器件中制造狗骨的方法，包括以下步骤。 提供了具有形成有STI的上硅层的半导体结构。 半导体结构具有LOGIC区域和其间具有缝合区域的DRAM区域。 在半导体结构上形成多晶硅层。 掺杂剂选择性地注入到DRAM区域内的多晶硅区域中，并且DRAM区域内的线圈区域的部分，以形成掺杂的多段，以及逻辑区域内的未掺杂的多段，以及缝合区域的部分 在LOGIC区域内。 在掺杂的多段和未掺杂的多段上形成硬掩模，并且被图案化以仅在DRAM区域内的字线掺杂的多段上形成至少一个图案化的第一硬掩模部分。 至少一个第二掩模层部分形成在LOGIC区域内的未掺杂的多段上，并且至少一个第三掩模层部分形成在DRAM区域内的线迹区域的部分中的掺杂多晶片段上。 蚀刻掺杂的多段和未掺杂的多段以在逻辑区内形成未掺杂的多边形逻辑门部; 在DRAM区域内的线圈区域的部分内的掺杂多晶骨; 和在DRAM区域内的掺杂多晶字线。 剥离第二和第三掩模层部分以暴露未掺杂的多边形逻辑门部分和掺杂的多晶骨。
-
9.发明授权Node process integration technology to improve data retention for logic based embedded dram 有权节点过程集成技术，以提高基于逻辑的嵌入式电脑的数据保留公开(公告)号：US06187659B1
公开(公告)日：2001-02-13
申请号：US09368861
申请日：1999-08-06
申请人： Tse-Liang Ying , Wen-Chuan Chiang , Cheng-Ming Wu , Yu-Hua Lee
发明人： Tse-Liang Ying , Wen-Chuan Chiang , Cheng-Ming Wu , Yu-Hua Lee
IPC分类号： H01L214763
CPC分类号： H01L27/10855 , H01L21/28525 , H01L21/76877 , H01L21/76885 , H01L21/76897
摘要： A new method is provided to create a gradated dopant concentration in the contact plug of DRAM devices whereby a high dopant concentration is present at the bottom of the plug and a low dopant concentration is present at the top of the plug. Two layers of dielectric are deposited; the upper layer serves as a layer to adjust the dopant concentration in the lower layer. This adjustment is done by Rapid Thermal anneal of both layers of dielectric. After the dopant concentration has been adjusted, the upper layer of dielectric is removed and the upper section of the contact node is formed using lightly doped poly. The high dopant concentration at the bottom of the contact plug results in low contact resistance between the plug and the underlying silicon substrate. A low dopant concentration at the top surface of the contact plug results in low oxidation of the surface of the plug.
摘要翻译： 提供了一种新的方法来在DRAM器件的接触插塞中产生渐变的掺杂剂浓度，由此在插塞的底部存在高的掺杂剂浓度，并且在插头的顶部存在低的掺杂剂浓度。 沉积两层电介质; 上层用作调整下层中的掺杂剂浓度的层。 这种调整是通过两层电介质的快速热退火进行的。 在调整掺杂剂浓度之后，去除电介质的上层，并且使用轻掺杂的多晶形成接触节点的上部。 接触插塞底部的高掺杂剂浓度导致插头和底层硅衬底之间的低接触电阻。 在接触塞顶表面的低掺杂剂浓度导致插塞表面的低氧化。
-
10.发明授权Reduction of the aspect ratio of deep contact holes for embedded DRAM devices 有权降低嵌入式DRAM器件深度接触孔的长宽比公开(公告)号：US06168984A
公开(公告)日：2001-01-02
申请号：US09419103
申请日：1999-10-15
IPC分类号： H01L218242
CPC分类号： H01L27/10888 , H01L27/10814 , H01L27/10894 , H01L28/84 , H01L28/91
摘要： A process for reducing the aspect ratio, for narrow diameter contact holes, formed in thick insulator layers, used to integrate logic and DRAM memory devices, on the same semiconductor chip, has been developed. The process of reducing the aspect ratio, of these contact holes, features initially forming, via patterning procedures, lower, narrow diameter contact holes, to active device regions, in the logic area, while also forming self-aligned contact openings to source/drain regions in the DRAM memory region. After forming tungsten structures, in the lower, narrow diameter contact holes, polycide bitline, and polysilicon capacitor structures, are formed in the DRAM memory region, via deposition, and patterning, of upper level insulator layers, and polysilicon and polycide conductive layers. Upper, narrow diameter openings, are then formed in the upper level insulator layers, exposing the top surface of tungsten structures, located in the lower, narrow diameter contact holes. The formation of upper tungsten structures, in the upper, narrow diameter contact openings completes the process of forming metal structures, in narrow diameter openings, with reduced aspect ratios, achieved via a two stage contact hole opening, and a two stage metal filling procedure.
摘要翻译： 已经开发了用于在相同的半导体芯片上将用于集成逻辑和DRAM存储器件的厚的绝缘体层中形成的窄直径接触孔的宽高比减小的方法。 减小这些接触孔的纵横比的过程，其特征在于，通过图案化步骤，在逻辑区域中最初形成较小的窄直径的接触孔到有源器件区域，同时还形成自对准的接触开口到源极/漏极 DRAM存储区域中的区域。 在形成钨结构之后，在下部窄直径的接触孔中，多晶硅位线和多晶硅电容器结构通过上层绝缘体层和多晶硅和多晶硅导电层的沉积和图案形成在DRAM存储区域中。 然后在上层绝缘体层中形成上部，小直径的开口，暴露位于下部较窄直径的接触孔中的钨结构的顶表面。 在上部窄直径接触开口中形成上部钨结构完成了通过两级接触孔开口形成的具有减小的纵横比的窄直径开口中的金属结构的形成和两阶段金属填充程序的过程。
-
-
-
-
-
-
-
-
-
搜索结果
44 条记录 (耗时 0.024 秒)
