公开(公告)号：US20100124891A1

公开(公告)日：2010-05-20

申请号：US12274167

申请日：2008-11-19

Applicant: I-Hsiang Lin ,  Tzu-wang Pan ,  Yi Zeng

Inventor： I-Hsiang Lin ,  Tzu-wang Pan ,  Yi Zeng

IPC: H03D5/00

CPC classification number: H04B1/525

Abstract: Exemplary embodiments include a frequency modulation (FM) transmitter and a non-FM receiver, which may be implemented on the same IC chip. The FM transmitter may include a digital FM modulator, a lowpass filter, an amplifier, and an LC tank circuit. The digital FM modulator may receive a digital input signal, perform FM modulation with the digital input signal, and provide a digital FM signal. The lowpass filter may filter the digital FM signal and provide a filtered FM signal. The amplifier may amplify the filtered FM signal and provide an output FM signal. The LC tank circuit may filter the output FM signal. The digital FM modulator may perform FM modulation by changing a variable divider ratio of a multi-modulus divider within a PLL. A delta-sigma modulator may receive the digital input signal and generate a modulator output signal used to obtain the variable divider ratio.

Abstract translation: 示例性实施例包括可以在同一IC芯片上实现的调频（FM）发射机和非FM接收机。 FM发射机可以包括数字FM调制器，低通滤波器，放大器和LC电路。 数字FM调制器可以接收数字输入信号，使用数字输入信号执行FM调制，并提供数字FM信号。 低通滤波器可以对数字FM信号进行滤波并提供滤波后的FM信号。 放大器可以放大经滤波的FM信号并提供输出FM信号。 LC振荡电路可以对输出的FM信号进行滤波。 数字FM调制器可以通过改变PLL内的多模式分频器的可变分频比来执行FM调制。 Δ-Σ调制器可以接收数字输入信号并产生用于获得可变分频比的调制器输出信号。

公开(公告)号：US20100097152A1

公开(公告)日：2010-04-22

申请号：US12254155

申请日：2008-10-20

Applicant: Cheng-Han Wang ,  Tzu-wang Pan

Inventor： Cheng-Han Wang ,  Tzu-wang Pan

IPC: G01R23/00 ,  H03L5/00

CPC classification number: H03H11/1291 ,  H03H11/1256

Abstract: An apparatus includes a filter and a gain control circuit. The filter receives and filters an input signal and provides an output signal in a first mode and operates as part of an oscillator in a second mode. The gain control circuit varies the amplitude of an oscillator signal from the oscillator in the second mode, e.g., by adjusting at least one variable gain element within the oscillator to obtain a target amplitude and/or non rail-to-rail signal swing for the oscillator signal. The apparatus may further include a bandwidth control circuit to adjust the bandwidth of the filter in the second mode. The bandwidth control circuit receives the oscillator signal, determines a target oscillation frequency corresponding to a selected bandwidth for the filter, and adjusts at least one circuit element within the filter to obtain the target oscillation frequency.

Abstract translation: 一种装置包括滤波器和增益控制电路。 滤波器接收并过滤输入信号并在第一模式中提供输出信号，并且在第二模式中作为振荡器的一部分进行操作。 增益控制电路在第二模式中改变来自振荡器的振荡器信号的振幅，例如，通过调整振荡器内的至少一个可变增益元件以获得目标振幅和/或非轨至轨信号摆幅 振荡器信号。 该装置还可以包括带宽控制电路，以在第二模式中调整滤波器的带宽。 带宽控制电路接收振荡器信号，确定与滤波器的选定带宽对应的目标振荡频率，并调整滤波器内的至少一个电路元件以获得目标振荡频率。

公开(公告)号：US06320444B1

公开(公告)日：2001-11-20

申请号：US09354644

申请日：1999-07-15

Applicant: Ravindra U. Shenoy ,  Tzu-wang Pan

Inventor： Ravindra U. Shenoy ,  Tzu-wang Pan

IPC: H03H1126

CPC classification number: H03L7/0995 ,  H03K3/0231 ,  H03K5/133 ,  H03K2005/00176 ,  H03K2005/00208 ,  H03L7/10

Abstract: An initial phase control for an oscillator such as a differential ring voltage-controlled oscillator is disclosed. The initial phase control generally comprises a current source circuit coupled to a first node of the delay cell and a current provider. The current source circuit and current provider are preferably selectively and synchronously in an on or off state such that when the current source circuit and current provider are in an on state, the current source circuit draws a current through the first node of the delay cell and the current provider provides current through a second node of the delay cell. A method for controlling a delay cell and an initial phase control for a differential ring oscillator having a plurality of delay cells in a ring configuration are also disclosed.

Abstract translation: 公开了一种用于诸如差分环压控振荡器的振荡器的初始相位控制。 初始相位控制通常包括耦合到延迟单元的第一节点和当前提供器的电流源电路。 电流源电路和电流提供器优选地选择性地和同步地处于导通或关断状态，使得当电流源电路和电流供应器处于导通状态时，电流源电路通过延迟单元的第一节点画出电流，并且 当前提供商通过延迟单元的第二节点提供电流。 还公开了一种用于控制具有环形结构中的多个延迟单元的差分环形振荡器的延迟单元和初始相位控制的方法。

公开(公告)号：US5479126A

公开(公告)日：1995-12-26

申请号：US483499

申请日：1995-06-07

Applicant: Tzu-Wang Pan ,  Jenn-Gang Chern

Inventor： Tzu-Wang Pan ,  Jenn-Gang Chern

IPC: H03L7/093 ,  H03L7/089 ,  H03L7/107 ,  H03K5/13 ,  H03K5/22

CPC classification number: H03L7/0893 ,  H03L7/0891 ,  H03L7/107 ,  H03L2207/04

Abstract: A timing acquisition circuit using a phase locked loop with programmable damping for either Type A or Type B phase detectors is described. In the damping scheme for a Type A phase detector, a resistance (R1) is simulated by adding an equivalent voltage Veff to the capacitor voltage. The equivalent voltage Veff is generated internally, so that programmable damping is made possible. In Type B phase detectors, a variable gain amplifier is used to control the effective resistance (R1) of the loop filter.

Abstract translation: 描述了使用具有针对A型或B型相位检测器的可编程阻尼的锁相环的定时采集电路。 在A型相位检测器的阻尼方案中，通过将等效电压Veff加到电容电压来模拟电阻（R1）。 等效电压Veff在内部产生，使得可编程阻尼成为可能。 在B型相位检测器中，使用可变增益放大器来控制环路滤波器的有效电阻（R1）。

公开(公告)号：US5467370A

公开(公告)日：1995-11-14

申请号：US217493

申请日：1994-03-24

Applicant: Richard G. Yamasaki ,  Tzu-Wang Pan

Inventor： Richard G. Yamasaki ,  Tzu-Wang Pan

IPC: H03H21/00 ,  G11B20/10 ,  H03H15/00 ,  H03H17/00 ,  H03M13/23 ,  H03M13/39 ,  H04B3/04 ,  H03H7/30 ,  G11B5/035

CPC classification number: G11B20/10009

Abstract: An improved adaptive three tap transversal equalizer for partial-response signaling. The invention reduces the complexity of the hardware, as well as reducing the sensitivity of the equalizer to gain and timing errors. The present invention employs an algorithm based on sample values around zero. The resulting decrease in average magnitude of the error results in decreased sensitivity to gain errors. The algorithm of the present invention improves cancellation of sample timing errors. In the present invention, the coefficient of an adaptive cosine equalizer is updated by integration of a stochastic gradient. To calculate the gradient, the product of the quantized output from the previous sample and the output from the present sample is summed together with the product of the output from the previous sample and the quantized output from the present sample. In addition, the equalizer output is masked such that values quantizing to non-zero values are discarded in the update algorithm. In systems employing separate adaptive loops for gain control, timing recovery and equalization, the amount of undesired loop interaction is much reduced from that of prior art methods.

Abstract translation: 一种用于部分响应信号的改进的自适应三抽头横向均衡器。 本发明降低了硬件的复杂性，同时降低了均衡器对增益和定时误差的敏感性。 本发明采用基于零附近的样本值的算法。 由此导致的误差的平均幅度的降低导致对增益误差的敏感性降低。 本发明的算法改进了采样定时误差的消除。 在本发明中，通过随机梯度的积分来更新自适应余弦均衡器的系数。 为了计算梯度，将来自先前样本的量化输出和当前样本的输出的乘积与来自先前样本的输出和当前样本的量化输出的乘积相加。 另外，均衡器输出被屏蔽，使得量化到非零值的值在更新算法中被丢弃。 在采用单独的自适应环路用于增益控制，定时恢复和均衡的系统中，与现有技术方法相比，不期望的环路相互作用量大大降低。

公开(公告)号：US08818282B2

公开(公告)日：2014-08-26

申请号：US13357830

申请日：2012-01-25

Applicant: Beomsup Kim ,  Tzu-Wang Pan ,  Young Gon Kim

Inventor： Beomsup Kim ,  Tzu-Wang Pan ,  Young Gon Kim

IPC: H04B1/00

CPC classification number: H03L7/0995 ,  H03L7/1976 ,  H04B1/403

Abstract: An integrated circuit is described. The integrated circuit includes a global positioning system core that generates a GPS clock signal using an inductor-capacitor voltage controlled oscillator. The integrated circuit also includes a transceiver core configured to use the GPS clock signal. The transceiver core may not include a voltage controlled oscillator.

Abstract translation: 描述了集成电路。 集成电路包括使用电感器电容器压控振荡器产生GPS时钟信号的全球定位系统核心。 集成电路还包括被配置为使用GPS时钟信号的收发机芯。 收发机芯可能不包括压控振荡器。

公开(公告)号：US08536947B2

公开(公告)日：2013-09-17

申请号：US12340142

申请日：2008-12-19

Applicant: Cheng-Han Wang ,  Tzu-wang Pan ,  Roger Brockenbrough

Inventor： Cheng-Han Wang ,  Tzu-wang Pan ,  Roger Brockenbrough

IPC: H03F3/45

CPC classification number: H03F3/45183 ,  H03F1/307

Abstract: A class AB amplifier with resistive level-shifting circuitry is described. In one exemplary design, the class AB amplifier includes an input stage, a resistive level-shifting stage, a class AB output stage, and a bias circuit. The input stage receives an input signal and provides a first drive signal. The resistive level-shifting stage receives the first drive signal and provides a second drive signal. The output stage receives the first and second drive signals and provides an output signal. The bias circuit generates a bias voltage for the resistive level-shifting stage to obtain a desired quiescent current for the output stage. In one exemplary design, the resistive level-shifting stage includes a transistor and a resistor. The transistor receives the bias voltage and provides the second drive signal. The resistor is coupled to the transistor and provides a voltage drop between the first and second drive signals.

Abstract translation: 描述了具有阻性电平移位电路的AB类放大器。 在一个示例性设计中，AB类放大器包括输入级，电阻电平转换级，AB类输出级和偏置电路。 输入级接收输入信号并提供第一驱动信号。 电阻电平转换级接收第一驱动信号并提供第二驱动信号。 输出级接收第一和第二驱动信号并提供输出信号。 偏置电路产生用于电阻电平移位级的偏置电压，以获得用于输出级的期望的静态电流。 在一个示例性设计中，电阻电平移位级包括晶体管和电阻器。 晶体管接收偏置电压并提供第二驱动信号。 电阻器耦合到晶体管并且在第一和第二驱动信号之间提供电压降。

公开(公告)号：US20130040583A1

公开(公告)日：2013-02-14

申请号：US13357830

申请日：2012-01-25

Applicant: Beomsup Kim ,  Tzu-Wang Pan ,  Young Gon Kim

Inventor： Beomsup Kim ,  Tzu-Wang Pan ,  Young Gon Kim

IPC: H04B1/40 ,  H04B1/38 ,  H03B5/08

CPC classification number: H03L7/0995 ,  H03L7/1976 ,  H04B1/403

Abstract: An integrated circuit is described. The integrated circuit includes a global positioning system core that generates a GPS clock signal using an inductor-capacitor voltage controlled oscillator. The integrated circuit also includes a transceiver core configured to use the GPS clock signal. The transceiver core may not include a voltage controlled oscillator.

Abstract translation: 描述了集成电路。 集成电路包括使用电感器电容器压控振荡器产生GPS时钟信号的全球定位系统核心。 集成电路还包括被配置为使用GPS时钟信号的收发机芯。 收发机芯可能不包括压控振荡器。

公开(公告)号：US08254849B2

公开(公告)日：2012-08-28

申请号：US12417512

申请日：2009-04-02

Applicant: Tzu-wang Pan ,  Yi Zeng ,  I-Hsiang Lin ,  Pushp K. Trikha ,  Jeremy D. Dunworth ,  Rahul Apte

Inventor： Tzu-wang Pan ,  Yi Zeng ,  I-Hsiang Lin ,  Pushp K. Trikha ,  Jeremy D. Dunworth ,  Rahul Apte

IPC: H04B1/06

CPC classification number: H04B1/3805 ,  H04B15/06

Abstract: An FM radio with a wide frequency range operates in a cell phone without interfering with the VCO of the RF transceiver. The FM transceiver generates a VCO signal whose frequency varies by less than ±7% from the midpoint of a narrow first range. A synthesizer signal is generated by dividing the VCO frequency by a first divisor such that the synthesizer frequency varies over a lower frequency second range. The VCO frequency is also divided by a second divisor such that the synthesizer frequency varies over a third range. The upper limit of the second range falls at the lower limit of the third range. The lower limit of the second range is 85.5 MHz and the upper limit of the third range is 108.0 MHz. By also using a third divisor, a synthesizer signal with a range of 76-108 MHz is generated from the narrow first frequency range.

Abstract translation: 具有宽频率范围的FM收音机在手机中工作，而不会干扰RF收发器的VCO。 FM收发器产生一个VCO信号，其频率从窄的第一范围的中点变化小于±7％。 通过将VCO频率除以第一因子来产生合成器信号，使得合成器频率在较低频率的第二范围内变化。 VCO频率也被第二除数除以使得合成器频率在第三范围内变化。 第二范围的上限落在第三范围的下限。 第二范围的下限为85.5MHz，第三范围的上限为108.0MHz。 通过使用第三除数，从窄的第一频率范围产生具有76-108MHz范围的合成器信号。

公开(公告)号：US08169270B2

公开(公告)日：2012-05-01

申请号：US12437462

申请日：2009-05-07

Applicant: Yi Zeng ,  Tzu-wang Pan ,  I-Hsiang Lin

Inventor： Yi Zeng ,  Tzu-wang Pan ,  I-Hsiang Lin

IPC: H03B5/12

CPC classification number: H03B5/1228 ,  H03B5/1212 ,  H03B5/1253 ,  H03B5/1265 ,  H03B5/1293

Abstract: A VCO (for example, in an FM receiver) includes an LC resonant tank. The LC resonant tank includes a coarse tuning capacitor bank and a fine tuning capacitor bank. The coarse tuning capacitor bank contains a plurality of digitally controlled coarse tuning capacitor elements, each providing a first capacitance value when active. The fine tuning capacitor bank contains a plurality of digitally controlled fine tuning capacitor elements, each providing a second capacitance value when active. To address the practical problem of capacitor mismatch, capacitance overlap throughout the VCO tuning range is created by selecting the first and second capacitance values such that the capacitance value of the fine capacitor bank is greater than the first capacitance value when all of the digitally controlled fine tuning capacitor elements of the fine capacitor bank are active.

Abstract translation: VCO（例如，在FM接收机中）包括LC谐振回路。 LC谐振槽包括一个粗调谐电容器组和一个微调电容器组。 粗调谐电容器组包含多个数字控制的粗调电容器元件，每个主调制电容器元件在有源时提供第一电容值。 微调电容器组包含多个数字控制的微调电容器元件，每个微调电容器元件在有源时提供第二电容值。 为了解决电容器失配的实际问题，通过选择第一和第二电容值来创建整个VCO调谐范围内的电容重叠，使得当全部数字控制的精细时，精细电容器组的电容值大于第一电容值 精细电容器组的调谐电容器元件是有效的。